ABSTRACT. One of the most fascinating areas of research is the strive for designing a neuromorphic or brain simulating system, where specialized algorithms run on a brain-inspired microprocessor may replicate the dynamical behavior of the vast network of synapse-coupled neurons. Current digital supercomputers are able to reproduce some of the brain functionalities, but, as more and more intelligent operations are emulated, the consequent increases in power consumption and integrated circuit area are somewhat unacceptable. These increases are due to the inefficient classical Von- Neumann architecture, which is at the basis of the machine design and is characterized by a rigid adherence to Boolean logic and, above all, by the separation between the physical location where data are stored, i.e. the memory, and the physical location where data processing takes place, i.e. the Computing Power Unit. In addition to that, complex integration of information performed by biological neural systems is based on several dynamical mechanisms. Among them, the most worth is the synchronization of neural activity. Synchronization of neural activity is also one of the proposed solutions to a widely discussed question in neuroscience: the binding problem, i.e. how our brain bind all the different data together to recognize objects. Despite remarkable progress has been made in the field of Neurophysiology and Nonlinear Dynamics needed to understand neural structures and interactions, current brain-simulating systems require high-computational capabilities to reproduce only a few brain functionalities.

The tutorial aims to present the fundamental theory of memristor oscillatory networks, their nonlinear dynamical properties, including synchronization, bifurcation phenomena and spatio-temporal pattern formation, for information processing tasks.

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ABSTRACT. In this work, we present a compact memristor model for bipolar neuromorphic ReRAM devices. The proposed model focuses on a behavioural high level description of the device, and it reproduces some of the most important characteristics (i.e. conductance, energy dissipation), using the number of pulses as the input variable instead of any electrical . Its functionality is shown by using it to model the behavior of three different ReRAM devices that were fabricated and measured at the CNR-IMM, Agrate Brianza. Considering a train of identical pulses as an input voltage signal consisting of $N$ pulses and where m is the pulse number. The conductance during depression or potentiation can be described.

ABSTRACT. Reinforcement learning (RL) has shown its viability to learn when an agent interacts continually with the environment to optimize a policy. This work presents a memristor-based deep reinforcement learning (Mem-DRL) system for on-chip training, where the learning process takes place in a dynamic cartpole environment. Memristor device variability is taken into account to make the study more realistic. The proposed system utilized an analog ReLu module to reduce analog to digital converter usage. The analog Mem-DRL system consumed 192 times less energy than an optimized digital FP16 computing system. Mem-DRL computed 9.27 GOPS and exhibited an energy efficiency of 23.8 TOPS/W.

ABSTRACT. Memristor crossbar-based neural networks perform parallel operation in the analog domain. Ex-situ training approach needs to program the predetermined resistance values in the memristor crossbar. Because of the stochasticity of the memristor devices, programming a memristor needs to read the device resistance value iteratively. Reading a single memristor in a crossbar (without isolation transistor) is challenging due to the sneak path current. Programming a memristor in a crossbar to either RON or ROFF state is relatively straightforward. A neural network implemented using higher precision weights provides higher classification accuracy compared to a Ternary Neural Network (TNN). This paper demonstrates the implementation of memristor-based neural networks using only the two resistance values (RON, ROFF). At the same time, it achieves higher weight precision. The experimental result shows that the proposed higher precision synapses are easy to program and provide better classification accuracy compared to a TNN.

ABSTRACT. Valence change mechanism (VCM)-based memristive devices are interesting candidates for computing in memory and neuromorphic applications. For these devices read noise is a characteristic which is influenced by a variety of factors like the switching mode, namely the area-dependent and the filamentary mode. In this paper we use TiOx -based devices as an example system exhibiting both modes. This allows to only investigate the effect of the modes while excluding other influences. We find that the read noise in the area-dependent mode is lower than for the filamentary mode and that abrupt current jumps are primarily seen for the filamentary mode. This has to be taken into account when choosing the right operation mode for a specific application.

ABSTRACT. Memristor-based analog Content Addressable Memories (aCAMs) offer robust parallel pattern look-up capabilities, significantly enhancing the scope of In-Memory Computing applications. This paper presents challenges of these analog circuits, which may occur during the inference, and proposes solutions to overcome them. Precisely, we investigate the impact of temperature-dependent behavior, CMOS process variations and memristor telegraph read noise. We demonstrate that the most challenging issue affecting memristors analog computing applications, namely read noise, is not a significant problem in aCAM. We introduce a framework that accounts for these combined distortions to define variability-aware aCAM windows and estimate the bit resolution of a CAM cell. We study how variations affect the inference accuracy of the IRIS classification dataset using our novel torchCAM model. We introduce a streamlined aCAM design featuring a memristor comparator for simplified input-to-reference comparison and a novel cell architecture with two symmetrical memristor comparator units.

ABSTRACT. The resistive random access memory (RRAM) is one of the promising technology based solutions for energy-efficient reconfigurable logic in memory (LiM) designs. In this paper, a Multi-Mode Configurable Physical Unclonable Function (MC-PUF) is proposed for secure RRAM-based LiM applications. The proposed MC-PUF can be configured to different working modes by adjusting the programming voltages of the corresponding RRAM. When the proposed MC-PUF is configured in a weak write mode, it exploits the inherent variations of an RRAM by adjusting the programming voltages to a switching probability of 50%. When the proposed MC-PUF is programmed in a normal reset voltage and configured in a parallel competition mode, it generates a response by selecting two parallel RRAMs. With the same number of RRAMs, the proposed MC-PUF generates more challenge-response pairs (CRPs) compared to conventional designs. The implementation of the MC-PUF on an RRAM crossbar array is presented. The results from both the experiment and simulation demonstrate that the proposed MC-PUF has good uniqueness, high reliability as well as excellent configurability.

ABSTRACT. The Cellular Nonlinear Network (CNN) is a powerful paradigm in analog computing. As pure-CMOS based CNN Universal Machine faces the von Neumann bottleneck, the integration of memristive devices with their non-volatile memory properties is of major interest. These networks are called Memristor-CNNs (M-CNNs). Moreover, the integration of memristors brings richer dynamics into the network, such that M-CNNs are highly suitable for neuromorphic computing tasks. This paper presents the experimental verification of a processing unit of an uncoupled M-CNN design with a valance change mechanism (VCM) based memristor. We outline a simple measurement strategy to study M-CNNs with real-world devices and provide compelling evidence that the results of the M-CNN processing element are stored in a non-volatile manner. This work further offers crucial insights into design considerations of M-CNN networks.

ABSTRACT. In the past two decades, the shift towards a distributed computing paradigm led our smart systems to become more and more interconnected. These systems need to elaborate increasingly amount of data while featuring low-power operation, area efficiency, and ability to interact with the external world in real time. Memristive technology, with its unique characteristics and capabilities, holds great promise for the design of such cognitive systems. The potential for energy-efficient and parallel computing, combined with the ability to integrate complex neural and synaptic dynamics within a single device, provides avenues for high-performance hardware implementations. Moreover, by offering volatile and non-volatile memory in a small footprint, enabling dense integration, and facilitating in-memory computing, memristive technology presents advantages that, if correctly combined with CMOS technology, can extend the functionality of current artificial intelligent systems.

In this talk, we discuss the challenges and the opportunities to realise memristive neuromorphic computing by developing novel hardware architectures and learning algorithms specifically tailored to best exploit the intrinsic properties of memristive technology. Indeed, we show that memristive technology offers vast potential, but its effective utilization relies on the synergetic development of memristive devices, circuits, and algorithms to create performing hardware cognitive systems.

ABSTRACT. This paper presents low power circuit design using dynamic gate diffusion input (GDI) technology in Carbon nanotube field effect transistor (CNTFET) technology. GDI technique offers low power with fewer transistor counts and less complexity of circuit and CNTFET technology offers low short channel effect (SCE). NAND and XOR gates-based full adder and two-bit multiplier is designed using the GDI technique and performance analysis is done for various parameters namely power consumption, delay, and power delay product (PDP). Results show that NAND gate-based circuits perform better than XOR-based circuits. Also dynamic GDI NAND gate-based circuits accounts for less power with more flexibility as compared to conventional CMOS-based NAND gate circuits.

ABSTRACT. Controlling of resistive switching properties by optical means opens the route to new optoelectronics that can be written optically and read electronically. In this work, we demonstrate optically controlled memristors realized with a hybrid material of vertically aligned zinc oxide nanorods (ZnO NRs) and poly(methyl methacrylate) (PMMA). In addition to electronic switching, the devices are switchable by optical means upon illumination with UV light. The hybrid memristors require no forming step and exhibit multilevel switching behavior achieved by controlling either the DC sweep voltage or the UV light power. The optical memristor exhibits irreversible switching for the Off state, which has an important application in the fabrication of cloned neural networks with pre-trained information. The work provides a promising pathway for the fabrication of simple-to-make and low-cost optoelectronic devices for memory and optically tuned neuromorphic computing applications.

ABSTRACT. We theoretically investigate the prospect of room temperature single qubit operation using a single Nitrogen (N) deep donor within Silicon (Si) quantum computer architecture. We quantitatively demonstrate the possible single electron shuttling between an isolated N-deep donor placed within Si matrix and corresponding dopant induced potential well at the Si / SiO2 interface by the interplay of externally applied electric and magnetic fields. Further, we have added a central cell correction potential to the composite Hamiltonian of the system for a robust description of various parameters associated towards the experimental realization of the proposed device. We also have analyzed and theoretically calculated all the external fields and important time scales involved in the process and their feasibility for the experimental purpose. In practice, we have theoretically demonstrated a room temperature single electron shuttling that in turn will cement the high temperature qubit transfer architecture.

ABSTRACT. Proteinoids are peptide-like molecules that arise from the combination of amino acids in pre-biotic environments. Recent studies have revealed distinctive electrical characteristics of proteinoids, such as the presence of voltage-gated ion channels, electrical switching capabilities, and the ability to modulate conductivity. Proteinoids possess properties that render them highly favourable as fundamental components for unconventional computing architectures inspired by biological systems. This study involved the synthesis of multiple proteinoids and the subsequent characterisation of their electrical properties through the use of impedance measurements. Proteinoids-based computing logic gates were developed through the integration of proteinoids and electrodes. We developed proteinoid neural networks capable of learning fundamental patterns by adjusting the proteinoid conductivity through training stimuli. Additionally, we have shown that a proteinoid mixture displays rudimentary capabilities for learning and memory. Our findings demonstrate the versatility of proteinoids as nanomaterials that can be utilised in innovative and unconventional computing systems. The utilisation of bio-derived electrical properties and self-assembly of proteinoids has the potential to facilitate the development of environmentally friendly and sustainable neuromorphic or evolutionary computing architectures. Our objective is to improve the complexity and performance of proteinoid computing systems for practical use in the future.

ABSTRACT. We report on the electrical effects of single and double polymer (polymethacrylate) barriers on polyethylene oxide (PEO) based memristors. The single barrier device with an active layer embedded with WS2 quantum dots is also investigated. The addition of a single PMA barrier yields multi cross point current-voltage hysteresis while the addition of embedded quantum dots removes multi-cross point behavior and shows repeatable uni-polar switching with the device starting in the low resistive state (LRS). The device shows some capability of reversible unipolar to bipolar operation as a function of applied voltage and device rest time. The addition of a double PMA barrier produces a reproducible unipolar switching behavior and a unipolar negative differential resistance behavior at higher voltage operation.

ABSTRACT. Reinforcement learning optimization of quantum circuits uses an agent whose goal is to maximize the value of a reward function that tells what is correct and what is wrong during the exploration of the search space. It is an open problem how to formulate reward functions that lead to fast and efficient learning. We propose an exponential reward functions which is sensitive to structural properties of the circuit. We benchmark our function on circuits with known optimum depths, and conclude that our function is reducing the learning time and improve the optimization. Our results are a next step towards fast, large scale optimization of quantum circuits.

ABSTRACT. This paper presents a strong physical unclonable function (PUF) based on the arbiter mechanism and spin orbit torque magnetic random access memory (SOT-MRAM). This proposed PUF can be easily reconfigured, with 2^32 challenge-response pairs (CRPs) generated during each reconfiguration. Meanwhile, the proposed PUF shows a strong resistance against typical machine learning modeling attacks.

ABSTRACT. Noise is one of the most challenging aspects of cellular nonlinear networks adversely affecting their functionality. Existing techniques to addressing the issues posed by noise are based on well-understood noise removal methods that have reached technical maturity and further have the disadvantage of limited success rates. A deeper understanding and modeling of noise dynamics and its origins are required for the efficient identification and resolution of problems in different network applications. The Stochastic template concept in this article can be beneficial in understanding and modeling noise dynamics in cellular nonlinear networks, which is critical for addressing challenges in network applications. In this paper, memristors functioning as synapses introduce noise into networks, and we conduct an initial investigation of a noisy network performing edge detection.

ABSTRACT. Formal verification techniques ensure completeness as opposed to simulation- based techniques. In general, the process of formal verification is computationally complex, and it is difficult to quantify the exact time and space complexities. Some of the recent works have shown that it is possible to achieve polynomial space and time complexities for verifying specific designs like arithmetic circuits. However, this cannot be directly extended to complex circuits like processors. A recent work has reported a formal verification method for the RISC-V processor with polynomial complexity, where only single-cycle instruction execution was considered and it was computation intensive. This method cannot be directly extended to multi-cycle operations, which are typical of most real processors. This paper introduces an improved data structure leading to Binary Decision Diagram (BDD) based Polynomial Formal Verification (PFV) with support for both single-cycle and multi-cycle operations. We use the MicroRV32 processor as a case study. Our method leads to significant improvement in runtime over the previous method. The entire process of verification can be carried out in polynomial space and time complexities for multi-cycle operations, which is the first such demonstration to the best of our knowledge.

ABSTRACT. We present a novel Clifford+T decomposition of a Toffoli gate. Our decomposition requires no SWAP gates in order to be implemented on 2D square lattices of qubits. This decomposition will enable shallower, more fault-tolerant quantum computations on both NISQ and error-corrected architectures. We present the derivation of the circuit, and illustrate the qubit mapping on a Sycamore-like architecture.