The Future of Hardware Technologies for Computing (abstract)

A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems (abstract)

Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds (abstract)

Post-Layout Optimization for Field-Coupled Nanotechnologies (abstract)

Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models (abstract)

LUT-based RRAM Model for Neural Accelerator Circuit Simulation (abstract)

Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study (abstract)

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning (abstract)

In-Memory Computing using Ferroelectric Transistors: Lessons Learnt and Future Trends (abstract)

Engineering memristors for memory, neuromorphic computing and beyond (abstract)

Organic semiconductors: from displays to neuromorphic (abstract)

Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters (abstract)

Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis? (abstract)

Non Volatile Operators Emulation Platform (abstract)

Neural Network Modeling Bias for Hafnia-based FeFETs (abstract)

Multiplexer Optimization for Adders in Stochastic Computing (abstract)

Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic (abstract)

Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences (abstract)

Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing (abstract)

A Robust Time-based Error-Proofing Readout Scheme for MRAM (abstract)

Hyper Dimensional Computing with Ferroelectric Tunneling Junctions (abstract)

Spin Wave Threshold Logic Gates (abstract)

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies (abstract)

Concept paper on novel radio frequency resistive switches (abstract)

Digital olfaction (abstract)

Memristor-based Oscillatory Platforms for Pattern Recognition: from nano-device to bioinspired algorithms (abstract)

TBA (abstract)

A Behavioural Compact Model for Programmable Neuromorphic ReRAM (abstract)

On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing (abstract)

Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights (abstract)

Impact of the switching mode on the read noise of ReRAM devices (abstract)

Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories (abstract)

An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation (abstract)

Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task (abstract)

Memristive and CMOS Technologies for Advanced Cognitive Systems (abstract)

Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology (abstract)

Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material (abstract)

Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature (abstract)

Electrical Properties of Proteinoids for Unconventional Computing Architectures (abstract)

Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots (abstract)

Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions (abstract)

A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM (abstract)

Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise (abstract)

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor (abstract)

A T-depth two Toffoli gate for 2D square lattice architectures (abstract)