ABSTRACT. Computing hardware is at a critical stage in its evolution. Our current AI computing demands, driven largely by the development of advanced Artificial Neural Networks (ANNs) whose compute demands currently double every 2-3 months, are rapidly becoming unsustainable. New approaches are needed, and memristive devices and systems are a set of technologies that offer significant promise. In this talk I will review the prospects for memristors to make a decisive contribution to the future of computing. I will address challenges around materials engineering, device design, and the adoption of new technologies by the CMOS industry.

ABSTRACT. Organic semiconductors are based on carbon compounds and allow an almost inexhaustible variety of materials. Devices based on organic semiconductors enable a variety of novel applications for flexible, lightweight, and environmentally friendly electronics. A first application success are OLED displays, which have already conquered a double-digit billion market and dominate the market in mobile phones.

In this talk, I introduce the material class of organic semiconductors and show with some examples from doping to organic solar cells the challenges of materials research and the implementation in products. Furthermore, vertical organic transistors with greatly improved properties are discussed, including bipolar transistors which open the GHz range for organic electronics. Finally, an outlook is given on a new form of neural networks based on organic semiconductors, allowing highly efficient neuromorphic computing approaches.

ABSTRACT. With the progression of Internet of Things, many novel consumer products such as wearable devices and disposable electronics requires flexibility, biocompatibility and ultra low-costs. However, these features can hardly be matched by traditional silicon-based electronics. In this regard, printed electronics becomes one of the most competitive candidate by offering the aforementioned properties thanks to its additive manufacturing process. To address fundamental signal-processing tasks, printed neuromorphic circuits, emulating the artificial neural networks, have received increasing attention, as they can achieve appealing computational capabilities by assembling simple elemental circuit primitives. However, many target applications for printed electronics are based on processing temporal sensory data, which is beyond the reach of existing printed neuromorphic circuits, since they lack components with time dependencies. To this end, this paper proposes a novel printed temporal processing block that combines existing circuit primitives with a sequence of learnable low-pass filters. We model the proposed circuit and proposed the corresponding training objective to enable the bespoke design of the circuits. Simulations on 15 benchmark time-series datasets reveal that, in comparison to existing printed neuromorphic circuits, the proposed circuits can effectively process temporal information by using 1.5× and 1.3× of device counts and power respectively. Moreover, the achieved classification accuracy reaches 98% of that from classic hardware-agnostic Elman recurrent neural networks.

ABSTRACT. Traditional computing is based on an engineering approach that imposes logical states and a computational model upon a physical substrate. Physical or material computing, on the other hand, harnesses and exploits the inherent, naturally-occurring properties of a physical substrate to perform a computation. To do so, reservoir computing is often used as a computing paradigm. In this review and position paper, we take stock of where the field currently stands, delineate opportunities and challenges for future research, and outline steps on how to get material reservoir to the next level. The findings are relevant for beyond CMOS and beyond von Neumann architectures, ML, AI, neuromorphic systems, and computing with novel devices and circuits.

ABSTRACT. The Von-Neumann bottleneck is one of the biggest problem to achieve higher computing performances and energy efficiency, especially in data centric applications. One of these application, the Internet of Things (IoT), is expanding at an impressive pace and is relying massively on sensors with limited energy to work. The emergence of new CMOS compatible technologies like ferroelectric field effect transistor (FeFET) allows to design new kind of Logic-in-Memory (LiM) operators. These non-volatile operators are expected to help overcoming the Von-Neumann Bottleneck as it will retain information thanks to the non volatility of the FeFET. The amount of data transfer will decrease thanks to this particularity. However, design of new computing operators is a long process. It is important to know if these operators are interesting to pursue into further development, which is why they need to be evaluated. To this extent, we present in this article a Non-volatile Operators Emulation Platform. the platform is based on the COMET RISC-V processor and use emulation to evaluate the impact of new non-volatile memories based operator on the processor performances in terms of number of instruction.

ABSTRACT. As the landscape of integrated electronics confronts fundamental limitations of conventional Complementary Metal-Oxide Semiconductor (CMOS) technology, the need for investigating novel post-CMOS device technologies in the context of deep learning has significantly grown, both in simulation and in prototyping. In this work, modeling bias – the difference between the test accuracy obtained by a reference network prototype and a simulated model of that prototype – is explored in the context of hafnia-based ferroelectric field effect transistor (FeFET) devices. Device operating conditions are investigated as a parameter for mitigating the impact of device-to-device variability on the underlying network performance. The computational framework includes a physics-based compact model with artificial variance to sample device data and a multivariate Kriging model to create jump table device models; this framework is a fast and efficient technique to model device populations for realistic neural network simulations. The performance of a 2-layer perceptron network – where each synapse is realized via an FeFET device in a crossbar-based training scheme – is investigated on the Modified National Institute of Standards and Technology (MNIST) dataset for classification. Results suggest that devices with low variability and high dynamic range generally attain good network performance, and that the device gate read voltage Vgs can be optimized to tradeoff between the two. This study elucidates novel insights regarding the capability of Hafnia-based FeFET devices as bit-limited synapses for classification problems, and thus, serves as an important guideline for future investigations into experimental prototypes of FeFET-based networks and other types of neuromorphic circuits.

ABSTRACT. This study presents an optimization algorithm for multiplexer (MUX)-based scaled addition for stochastic computing (SC). Accumulation operation can be performed in SC using a MUX unit. Cascaded structures of 2^m-to-1 MUXs are used for the accumulation of multiple terms. Optimizing these designs holds significance in cases of accumulating a large number of inputs. The depth of the cascaded MUXs varies with m, affecting the hardware cost, delay, and accuracy. The proposed algorithm performs stage-wise optimization of m. Evaluation results show a lower hardware cost and a higher accuracy compared to the standard MUX-based SC addition using 2-to-1 MUXs for SC-based neural networks.

ABSTRACT. Silicon Dangling Bonds (SiDBs) constitute a beyond-CMOS computational nanotechnology platform that enables higher integration density and lower power consumption than contemporary CMOS nodes. Recent manufacturing breakthroughs in the domain sparked the interest of academia and industry alike in the race for a green computation future at the nanoscale. However, as the fabrication of SiDBs requires atomic precision, SiDB logic systems are inherently susceptible to environmental defects and material variations, which inevitably occur. The Operational Domain is a methodology to evaluate the resilience of SiDB logic against physical parameter variations. However, state-of-the-art implementations require a quadratic number of exponentially complex physical simulator calls to assess the operational domain. This paper presents two novel algorithms to obtain operational domains in an efficient fashion: one based on flood fill, and one based on contour tracing. Experimental evaluations confirm that they reduce the number of required simulator calls by 70.87% and 95.29%, respectively. Particularly contour tracing achieves the shift from a quadratic to a linear relation, thereby reducing the complexity and paving the way for realizing reliable SiDB-based computing systems.

ABSTRACT. In stochastic computing (SC), data is represented using random bitstreams. The efficiency and accuracy of SC systems rely heavily on the stochastic number generator (SNG), which converts data from binary to stochastic bit-streams. While previous research has shown the benefits of using low-discrepancy (LD) sequences like Sobol and Halton in the SNG, the potential of other well-known random sequences remains unexplored. This study investigates new random sequences for potential use in SC. We find that Van Der Corput (VDC) sequences hold promise as a random number generator for accurate and energy-efficient SC, exhibiting intriguing correlation properties. Our evaluation of VDC-based bit-streams includes basic SC operations (multiplication and addition) and image processing tasks like image scaling. Our experimental results demonstrate high accuracy, reduced hardware cost, and lower energy consumption compared to state-of-the-art methods.

ABSTRACT. RRAM-enabled in-memory computing (IMC) is regarded as a promising solution for breaking the von Neumann bottleneck. Using RRAM-based IMC to construct heterogeneous computing systems can fully leverage the advantages of both digital and IMC platforms. Critical challenges are effectively managing the dataflows between the digital system and the analog IMC and providing a standard for communication. In this paper, from the perspective of hardware instruction execution, we designed a general RRAM-enabled analog instruction set architecture compatible with digital computing. These instructions adopted the vector-based computing concepts in RISC-V, and the examples compatible with RISC-V vector extension are demonstrated in detail. A tile-processing unit-array three-level architecture is also devolved to support the instruction execution. The hardware estimations are performed on 65 nm technology. Results indicate that the total activated power of the activated processing unit is 8.64 mW which is 4.9 times smaller than PUMA and 33.4 times smaller than ISAAC. The energy efficiency reaches 1190.7 GOPS/W, 1.42$\times$ and 3.12$\times$ compared with PUMA and ISAAC, respectively. Furthermore, as the analog and digital computing frequency increases, the peak energy efficiency can reach 40 TOPS/W which enables the future general use of the IMC-based heterogeneous system.

ABSTRACT. A time-based readout scheme with adjustable time resolution for magnetic random access memory (MRAM) is proposed. An improved error-proofing circuit utilizing phase detector (PD) is also designed to reduce bit error rate (BER). The strong robustness of the proposed circuits is verified using Monte Carlo simulations.

ABSTRACT. Hyper Dimensional Computing is a new approach in artificial intelligence (AI). The specific requirements of massive parallel readout operation during HDC inference makes the high-impedance ferroelectric tunneling junction (FTJ) devices a very interesting candidate for the hardware realization of a HDC accelerator. Therefore, we propose to research both, the technological and the architectural constraints when bringing together this two distinct concepts from the architectural and the devices perspective.

ABSTRACT. While Spin Waves (SW) interaction provides natural support for low power Majority (MAJ) gate implementations many hurdles still exists on the road towards the realization of practically relevant SW circuits. In this paper we leave the SW interaction avenue and propose Threshold Logic (TL) inspired SW computing, which relies on successive phase rotations applied to one single SW instead of on the interference of an odd number of SWs. After providing a short TL inside we introduce the SW TL gate concept and discuss the way to mirror TL gate weight and threshold values into physical phase shifter's parameters. Subsequently, we design and demonstrate proper operation of a SW TL based Full Adder (FA) by means of micro-magnetic simulations. We conclude the paper by providing inside on the potential advantages of our proposal by means of a conceptual comparison of MAJ and TL based FA implementations.

ABSTRACT. Multi-valued logic (MVL), characterized by more than two possible logic states, presents distinct advantages compared to conventional Boolean logic. Novel post-CMOS technologies, particularly memristive and bio-sensitive devices, exhibit compelling attributes that make them promising candidates for realizing MVL computing components. To assess the viability of these devices, we delve into key aspects of Memristive and ISFETs, including their state transition dynamics, multi-level functionality, and compatibility with CMOS manufacturing processes. Through this investigation, we successfully demonstrate the practical implementation of ternary arithmetic MVL gates utilizing memristive and bio-sensitive devices. Our findings affirm that these innovative devices hold the potential to serve as MVL computing elements effectively.

ABSTRACT. For reconfigurable radios where the signals can be easily routed from one band to another band, new radiofrequency switches (RF) are a fundament. The main factor driving the power consumption of the reconfigurable intelligent surface (RIS) is the need for an intermediate device with static power consumption to maintain a certain surface configuration state. Since power usage scales quadratically with the RIS area, there is a relevant interest in mitigating this drawback so that this technology can be applied to everyday objects without needing such a high intrinsic power consumption. Current switch technologies such as PIN diodes, and field effect transistors (FETs) are volatile electronic devices, resulting in high static power. In addition, dynamic power dissipation related to switching event is also considerable. Regarding energy efficiency, non-volatile radio frequency resistive switch (RFRS) concept may be better alternative solution due to several advantages: smaller area, zero-hold voltage, lower actuation bias for operation, short switching time, scalability and capable to be fabricated in the backend-of-line of standard CMOS process.

ABSTRACT. Olfaction, an ancient sensory system, provides intricate information about the environment. In emulation of this biological process, neuromorphic devices in conjunction with machine learning algorithms, endeavor to replicate and digitize the olfactory capabilities. This presentation focuses on the gas discrimination and identification capabilities of neuromorphic nanosensors. These nanosensors, constructed with functionalized nano materials, were integrated into multi-channel gas sensor devices, and their sensing signals were recorded upon exposure to diverse gases. The temporal characteristics of the gases were subsequently extracted from the sensing signals and input into a machine learning algorithm to discern and identify the specific gases. The resulting electronic olfaction system demonstrates outstanding gas identification performance across various gases. This innovative platform has the potential to downsize electronic noses, digitize olfactory information, and distinguish a range of gases and volatile organic compounds (VOCs). Applications include pathogen detection, environmental monitoring, and disease diagnosis.