TALK KEYWORD INDEX
This page contains an index consisting of author-provided keywords.
4 | |
4T1R cell | |
A | |
activation | |
Adaptive Test | |
advanced burn-in | |
AI | |
AI As A Service | |
analog | |
analog fault model | |
analog security | |
Anomaly Detection | |
At-speed Capture | |
ATE | |
ATPG | |
autoencoder | |
automatic test pattern generation | |
Automotive | |
Automotive Applications | |
Automotive Test | |
B | |
benchmark | |
binary RRAM | |
BIST | |
Bit-error-rate (BER) | |
Board-level functional test | |
boundary model | |
Buck Converter | |
burn-in | |
C | |
Causal Learning | |
Cell-aware | |
Cell-aware test | |
Chip Optimization | |
classification | |
CNN | |
Code-coverage | |
Complex IPs | |
complex SoCs | |
Convolutional Neural Network | |
Counterfeit electronics | |
cross-layer resilience | |
crossbar | |
current sensor | |
D | |
Data Analytics | |
Data Mining | |
debug | |
debug defect parts per million | |
Deep Learning | |
Deep neural network | |
defect modeling | |
Delay testing | |
Delay Variability | |
Design For Manufacturability | |
design for test | |
device-aware | |
DFT | |
Digital Acoustofluidic Biochip | |
Digital microfluidics | |
DL | |
DMFB | |
Domain adaptation | |
Dynamic Partial Reconfiguration | |
dynamic random access memory (DRAM) | |
E | |
Early Design Space Exploration | |
EDA | |
eFuse configuration | |
Embedded BIST and DFT | |
embedded-test | |
Error Correction | |
Error Detection | |
F | |
failure binning | |
Faster-than-at-speed test | |
fault coverage | |
Fault diagnosis | |
Fault isolation | |
Fault model | |
fault modeling | |
Fault Tolerance | |
Fault-recovery | |
FPGA | |
Freedom from Interference | |
functional broadside tests | |
Functional Safety | |
Functional Safety (FuSa) | |
Functional Test | |
functional test sequences | |
G | |
gate-exhaustive faults | |
Genetic Algorithm | |
GP-GPU | |
Graphic processing unit | |
H | |
Hardware Security | |
hierarchical test | |
high-speed interface testing | |
I | |
ICL | |
IEEE Standard 1500 | |
IEEE Std. 1149.1 | |
IEEE Std. 1687 | |
IEEE Std. P1687.1 | |
IJTAG | |
image completion | |
image-processing | |
InFO WLCSP | |
Integrated Voltage Regulators | |
Intellectual property protection | |
IP | |
IPD | |
IR Drop Prediction | |
J | |
jitter injection | |
K | |
Knowledge transfer | |
L | |
latent defects | |
latent space | |
Lithographic Hotspot Detection | |
logic built-in self-test (LBIST) | |
logic diagnosis | |
Logic Locking | |
Logic test chip | |
Low Dropout Regulator (LDO) | |
M | |
Machine Learning | |
magnetic sensor | |
MBIST | |
MEDA Biochip | |
Memory BIST | |
memory testing | |
Mixed-Criticality | |
Multi-cell characterization | |
Multi-core System-on-Chip | |
Multi-pattern test generation | |
N | |
NAND Flash | |
O | |
Obfuscation | |
On-Chip Test Compression | |
On-line Testing | |
Open defects | |
optimization | |
overkill | |
P | |
package on package (PoP) | |
partition design | |
Physically-Aware DFT | |
Power Efficiency | |
Power Loss Modeling | |
Power Supply Rejection Ratio (PSRR) | |
PPA | |
process variation | |
production testing | |
pulse amplitude modulation | |
Q | |
quality | |
R | |
Random forest | |
Rapid Single-Flux-Quantum (RSFQ) | |
RCS | |
reconfigurability | |
Reconfigurable Scan Networks | |
Recycled counterfeit | |
redistribution layer (RDL) | |
Register Transfer Level (RTL) | |
reliability | |
Resilience | |
robust systems | |
rram | |
RTL | |
S | |
Safety | |
Safety-critical Applications | |
SAT attack | |
Satisfiability modulo theories | |
scan-based testing | |
Security Validation | |
Self-diagnosis | |
Self-repair | |
sensor test | |
Side-Channel Attacks | |
Simulation | |
Simultaneous Switching Noise | |
small delay defect | |
Small-delay fault | |
sobel | |
soft errors | |
Software Test Library | |
SOTIF (Safety of the Intended Functionality) | |
standard-cells | |
Stochastic compaction | |
stress | |
Structrual Test | |
structured test | |
stt-mram | |
subtle anomalies | |
Superconductivity Electronics | |
supply-chain attacks | |
Synthetic Layout Generation | |
System Level Test | |
T | |
test | |
test application time | |
test compaction | |
test generation | |
Test Optimization | |
test points | |
Test Resource Partitioning | |
test response compaction | |
Test Time Reduction | |
testing | |
Timing Failures | |
Timing slack | |
transition faults | |
Tri-Modular redundancy (TMR) | |
U | |
UART | |
underkill | |
undetectable faults | |
V | |
VAE | |
Virtual Memory Container (VMC) | |
Virtual Memory Wrapper (VMW) | |
VR Characterization | |
Vstress | |
W | |
wafer defect diagnosis | |
wafer defect maps | |
Wafer Image Classification | |
wafer test | |
X | |
X-handling | |
Y | |
Yield learning |