ITC 2019: INTERNATIONAL TEST CONFERENCE 2019

This page contains an index consisting of author-provided keywords.

4
4T1R cell	Hardware Fault Tolerance for Binary RRAM Crossbars
A
activation	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Adaptive Test	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
advanced burn-in	IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
AI	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
AI As A Service	Deploying A Machine Learning Solution As A Surrogate
analog	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
analog fault model	Efficient Analog Defect Simulation
analog security	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Anomaly Detection	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
At-speed Capture	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
ATE	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
ATPG	Characterization of Locked Combinational Circuits via ATPG
autoencoder	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
automatic test pattern generation	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Automotive	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers Resiliency of automotive detection networks on GPU architectures
Automotive Applications	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Automotive Test	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
B
benchmark	Efficient Analog Defect Simulation
binary RRAM	Hardware Fault Tolerance for Binary RRAM Crossbars
BIST	A Hybrid Space Compactor for Adaptive X-Handling
Bit-error-rate (BER)	A Framework for Design of Self-Repairing Digital Systems
Board-level functional test	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
boundary model	IPP: Applications of Hierarchical Test
Buck Converter	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
burn-in	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
C
Causal Learning	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Cell-aware	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Cell-aware test	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Chip Optimization	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
classification	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug
CNN	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Code-coverage	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Complex IPs	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
complex SoCs	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Convolutional Neural Network	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Counterfeit electronics	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
cross-layer resilience	Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
crossbar	Hardware Fault Tolerance for Binary RRAM Crossbars
current sensor	A New Test Method for the Testing Large Current Magnetic Sensors
D
Data Analytics	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Data Mining	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
debug	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
debug defect parts per million	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug
Deep Learning	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Deep neural network	Resiliency of automotive detection networks on GPU architectures
defect modeling	Device-Aware Testing: A New Test Approach Towards DPPB
Delay testing	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Delay Variability	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
Design For Manufacturability	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
design for test	IPP: Applications of Hierarchical Test Efficient Analog Defect Simulation
device-aware	Device-Aware Testing: A New Test Approach Towards DPPB
DFT	A Hybrid Space Compactor for Adaptive X-Handling
Digital Acoustofluidic Biochip	Structural and Functional Test Methods for Digital Acoustofluidic Biochips
Digital microfluidics	Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
DL	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
DMFB	Structural and Functional Test Methods for Digital Acoustofluidic Biochips Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network
Domain adaptation	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Dynamic Partial Reconfiguration	A Framework for Design of Self-Repairing Digital Systems
dynamic random access memory (DRAM)	IPP: High Quality Test Methodology for Highly Reliable Devices
E
Early Design Space Exploration	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
EDA	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
eFuse configuration	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
Embedded BIST and DFT	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
embedded-test	Test Time and Area Optimized BIST Scheme for Automotive ICs
Error Correction	Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Error Detection	Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
F
failure binning	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Faster-than-at-speed test	A Hybrid Space Compactor for Adaptive X-Handling
fault coverage	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Fault diagnosis	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Fault isolation	A Framework for Design of Self-Repairing Digital Systems
Fault model	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
fault modeling	Device-Aware Testing: A New Test Approach Towards DPPB
Fault Tolerance	Hardware Fault Tolerance for Binary RRAM Crossbars Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Fault-recovery	Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network
FPGA	A Framework for Design of Self-Repairing Digital Systems
Freedom from Interference	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
functional broadside tests	Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
Functional Safety	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach Test Time and Area Optimized BIST Scheme for Automotive ICs
Functional Safety (FuSa)	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Functional Test	Structural and Functional Test Methods for Digital Acoustofluidic Biochips
functional test sequences	Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
G
gate-exhaustive faults	Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults
Genetic Algorithm	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
GP-GPU	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Graphic processing unit	Resiliency of automotive detection networks on GPU architectures
H
Hardware Security	Characterization of Locked Combinational Circuits via ATPG
hierarchical test	IPP: Applications of Hierarchical Test
high-speed interface testing	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
I
ICL	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
IEEE Standard 1500	IPP: Applications of Hierarchical Test
IEEE Std. 1149.1	IEEE Std. P1687.1: translator and protocol
IEEE Std. 1687	IEEE Std. P1687.1: translator and protocol
IEEE Std. P1687.1	IEEE Std. P1687.1: translator and protocol
IJTAG	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network
image completion	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
image-processing	IPP: High Quality Test Methodology for Highly Reliable Devices
InFO WLCSP	IPP: High Quality Test Methodology for Highly Reliable Devices
Integrated Voltage Regulators	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Intellectual property protection	Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
IP	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
IPD	IPP: High Quality Test Methodology for Highly Reliable Devices
IR Drop Prediction	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
J
jitter injection	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
K
Knowledge transfer	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
L
latent defects	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
latent space	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Lithographic Hotspot Detection	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
logic built-in self-test (LBIST)	Test Time and Area Optimized BIST Scheme for Automotive ICs
logic diagnosis	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Logic Locking	Characterization of Locked Combinational Circuits via ATPG
Logic test chip	Improving Test Chip Design Efficiency via Machine Learning
Low Dropout Regulator (LDO)	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
M
Machine Learning	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip Deploying A Machine Learning Solution As A Surrogate
magnetic sensor	A New Test Method for the Testing Large Current Magnetic Sensors
MBIST	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
MEDA Biochip	Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network
Memory BIST	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
memory testing	Device-Aware Testing: A New Test Approach Towards DPPB
Mixed-Criticality	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Multi-cell characterization	Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic
Multi-core System-on-Chip	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Multi-pattern test generation	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
N
NAND Flash	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
O
Obfuscation	Characterization of Locked Combinational Circuits via ATPG
On-Chip Test Compression	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
On-line Testing	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Open defects	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
optimization	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
overkill	IPP: High Quality Test Methodology for Highly Reliable Devices
P
package on package (PoP)	IPP: High Quality Test Methodology for Highly Reliable Devices
partition design	IPP: High Quality Test Methodology for Highly Reliable Devices
Physically-Aware DFT	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Power Efficiency	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Power Loss Modeling	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Power Supply Rejection Ratio (PSRR)	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
PPA	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
process variation	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
production testing	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
pulse amplitude modulation	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
Q
quality	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
R
Random forest	Improving Test Chip Design Efficiency via Machine Learning
Rapid Single-Flux-Quantum (RSFQ)	Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic
RCS	Hardware Fault Tolerance for Binary RRAM Crossbars
reconfigurability	Hardware Fault Tolerance for Binary RRAM Crossbars
Reconfigurable Scan Networks	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL Security Compliance Analysis of Reconfigurable Scan Networks
Recycled counterfeit	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
redistribution layer (RDL)	IPP: High Quality Test Methodology for Highly Reliable Devices
Register Transfer Level (RTL)	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
reliability	IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
Resilience	Resiliency of automotive detection networks on GPU architectures
robust systems	Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
rram	Device-Aware Testing: A New Test Approach Towards DPPB
RTL	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
S
Safety	Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Safety-critical Applications	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
SAT attack	Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
Satisfiability modulo theories	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
scan-based testing	Test Time and Area Optimized BIST Scheme for Automotive ICs
Security Validation	Security Compliance Analysis of Reconfigurable Scan Networks
Self-diagnosis	A Framework for Design of Self-Repairing Digital Systems
Self-repair	A Framework for Design of Self-Repairing Digital Systems
sensor test	A New Test Method for the Testing Large Current Magnetic Sensors
Side-Channel Attacks	Security Compliance Analysis of Reconfigurable Scan Networks
Simulation	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Simultaneous Switching Noise	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
small delay defect	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Small-delay fault	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
sobel	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
soft errors	Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
Software Test Library	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
SOTIF (Safety of the Intended Functionality)	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
standard-cells	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Stochastic compaction	A Hybrid Space Compactor for Adaptive X-Handling
stress	IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
Structrual Test	Structural and Functional Test Methods for Digital Acoustofluidic Biochips
structured test	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
stt-mram	Device-Aware Testing: A New Test Approach Towards DPPB
subtle anomalies	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Superconductivity Electronics	Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic
supply-chain attacks	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Synthetic Layout Generation	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
System Level Test	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
T
test	IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
test application time	Test Time and Area Optimized BIST Scheme for Automotive ICs
test compaction	Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
test generation	Device-Aware Testing: A New Test Approach Towards DPPB Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
Test Optimization	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
test points	Test Time and Area Optimized BIST Scheme for Automotive ICs
Test Resource Partitioning	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
test response compaction	A Hybrid Space Compactor for Adaptive X-Handling Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Test Time Reduction	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
testing	Device-Aware Testing: A New Test Approach Towards DPPB
Timing Failures	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
Timing slack	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
transition faults	Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
Tri-Modular redundancy (TMR)	A Framework for Design of Self-Repairing Digital Systems
U
UART	IEEE Std. P1687.1: translator and protocol
underkill	IPP: High Quality Test Methodology for Highly Reliable Devices
undetectable faults	Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults
V
VAE	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
Virtual Memory Container (VMC)	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Virtual Memory Wrapper (VMW)	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
VR Characterization	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Vstress	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
W
wafer defect diagnosis	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
wafer defect maps	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Wafer Image Classification	Deploying A Machine Learning Solution As A Surrogate
wafer test	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
X
X-handling	A Hybrid Space Compactor for Adaptive X-Handling
Y
Yield learning	Improving Test Chip Design Efficiency via Machine Learning

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