ABSTRACT. Characterization of digital library cells under a range of open defect sizes is investigated. The necessity of multi-pattern tests to expose certain defects is demonstrated via circuit simulation, and a faster switch-level approach is proposed.

ABSTRACT. As the Register Transfer Level (RTL) designs are more complicated, debugging becomes a major bottleneck in the design process. To make debugging more efficient, failure binning aims at grouping failure traces caused by the same error source together so that designers can focus on one bug at one time. However, as there are multiple bugs in a design, behaviors exhibited by failure traces are diverse and severely confuse designers. One error source may result in different appearances subject to different activation conditions. In addition, different error sources may also exhibit similar appearances among the limited number of failure traces. In this work, we propose an autoencoder-based failure binning engine name FAE for debugging RTL designs more efficiently. The autoencoders extract meaningful representations from the sparse and high-dimensional feature space to the latent space with good properties for clustering. Superior to prior works, FAE provides confidence ranks between bins and in a bin to clearly guide designers during debugging. Experimental results show that FAE can drive bins of higher purity under an acceptable number of bins than prior works, dropping only few less-informative failures. Evaluated by three common metrics for clustering, FAE also achieves averagely 13.1% improvement in purity, 25.0% improvement in NMI and 18.2% improvement in ARI, respectively. Most of all, we demonstrate that our method has good potential to conquer sparse and high-dimensional feature space which is common in EDA data. As a result, the proposed autoencoder-based engine, FAE, applies machine learning to extract useful information from diverse failure traces and is effective on failure binning with more focused debugging.

ABSTRACT. Dynamic compaction approaches for scan tests are not applicable to functional broadside tests. Instead, this paper compacts a functional test sequence from which functional broadside tests are extracted. Compaction is performed without sequential fault simulation.

ABSTRACT. High integration densities and design complexity make board-level functional fault identification extremely difficult. Machine-learning techniques can identify functional faults with high accuracy, but they require a large volume of data to achieve high prediction accuracy. This drawback limits the effectiveness of traditional machine-learning algorithms for training a model in the early stage of manufacturing, when only a limited amount of fail data and repair records are available. We propose a diagnosis workflow that utilizes domain adaptation to transfer the knowledge learned from a mature board to a new board in the ramp-up phase. First, a metric is designed to evaluate the similarity between products, and based on the calculated value of the similarity, either a homogeneous or a heterogeneous domain adaptation algorithm is selected. Second, these domain adaptation algorithms utilize information from both the mature and the new boards with carefully designed domain-alignment rules and train a functional fault identification classifier. Three complex boards in volume production and one new board in the ramp-up phase are used to validate the proposed domain-adaptation approach in terms of the diagnosis accuracy.

ABSTRACT. This paper introduces a new testing approach. It is based on incorporating the impact of physical defects on device electrical parameters before performing circuit/fault simulation. The approach is demonstrated both for RRAM and STT-MRAM.

ABSTRACT. The IEEE Std. P1687.1 working group is currently exploring alternatives to IEEE Std. 1149.1 test access port (TAP) as the interface between the boundary of integrated circuits (ICs) and IEEE Std. 1687 networks. In this paper, we investigate the use of universal asynchronous receiver-transmitter (UART) to access IEEE Std. 1687 networks. We have developed a protocol to describe the information transported over UART and a hardware component to translate (retarget) information between UART and IEEE Std. 1687. The objective is to minimize the amount of information transported over UART and the area of the hardware component while maintaining the flexibility to access an arbitrary combination of instrument in the IEEE Std. 1687 network. We have developed software for the protocol translation, implemented the hardware component and IEEE Std. 1687 networks of different sizes in an field-programmable gate array (FPGA). For comparison, we developed a number of alternatives, all implemented on FPGA. The experimental results show that proposed scheme gives low overhead in terms of transported information (data) and low area of the hardware component.

ABSTRACT. Automotive designs require very high manufacturing test coverage as well as high quality self-test solutions. They are also constrained by limited test pins and cost of test. Test Compression and logic built-in self-test (LBIST) are proven DFT solutions to address the automotive test and safety requirements but their high impact to backend physical implementation can be a huge barrier to successful adoption. Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations in Physical DFT Synthesis to solve routing congestion and area issues from traditional discrete approaches and paves the road to high-quality test. On a sample design, area savings of 35-47%, and scan wirelength savings of 63-77% for the same scan chain length can be achieved. Also, with the same area and wirelength budget as traditional implementations, the test application time can be reduced by half to reduce the overall cost of test for the same test coverage.

ABSTRACT. Automotive microcontrollers demand extremely high reliability requirements. Burn-In (BI) stress has been proven to be effective to screen out early life failures via voltage and temperature acceleration and becomes a quality requirement for automotive electronics. However, as feature size continues to scale down, performing BI stress on packaged parts have started to run into challenges including increased risks of thermal runaway and overstress, together with continuously increased cost and cycle time. A more effective and efficient product stress and test flow to achieve better quality with less cost, namely, Advanced Burn-In (ABI), is presented in this paper. With enhanced wafer level stress and enhanced Advanced Outlier Limit (AOL) algorithms applied to wafer level parametric tests before and after the stress, ABI enables us to eliminate package BI on majority of parts on each wafer, which reduces cost and cycle time but more importantly improves quality at the same time. It has been successfully implemented on multiple automotive products at NXP with superb quality – e.g., on a large volume product, we have achieved unparalleled quality at 42 PPB (fail Parts-Per-Billion) with over 46 million parts shipped in last 3 years with ABI.

ABSTRACT. The emergence of assisted and autonomous vehicles not only increases the number of integrated circuits in new cars, but also drives the automotive IC industry into quality levels of 10 PPB and below. The test and design methodology currently used to develop automotive mixed-signal integrated circuits, however, is not sufficient to achieve this goal. In particular does it not allow to activate and detect all latent defects, which are a significant cause of vehicle failures in the field. This paper discusses whether full burn-in will be needed in order to meet the quality goal, or whether Vstress in combination with a defect coverage activation will do the job.

ABSTRACT. Cell-aware test (CAT) explicitly targets realistic cell-internal manufacturing defects. The CAT flow from Cadence includes three steps, viz. (1) defect location identification, (2) defect characterization, and (3) cell-aware ATPG. This paper reports on the first-ever application of the CAT tool flow on an experimental standard-cell library in iN5, imec’s advanced 3nm CMOS technology node. We describe the innovations in this technology node with a bearing on CAT results. For the whole library, we reduce 73.5% defect count for defect characterization based on equivalence of defect effect on cells’ functionality. We also demonstrate the number of defect locations decrease in the iN5 cells compared with cells from the Cadence GPDK45 45nm library, but the reduced defect count for simulation is the same. Defect coverage of the iN5 cells is higher than the GPDK045 cells. Two algorithms are applied on defect-detection matrices (DDMs) in which the defect simulation results are encoded to optimize cell-aware ATPG results. A first algorithm identifies don’t-care bits for cell patterns to reduce the ATPG effort of generating a circuit test pattern. A second algorithm selects, at cell level, a subset of preferential patterns that jointly provide full fault-coverage at a minimized care-bit sum. The minimized numbers of care bits of both libraries are almost the same.