ITC 2019: INTERNATIONAL TEST CONFERENCE 2019

A
Abdollahian, Ayub	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Abotbol, Yehonatan	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Abraham, Jacob	Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Abuellil, Amr	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Atteya, Ahmed	Security Compliance Analysis of Reconfigurable Scan Networks
Aziza, Hassen	Device-Aware Testing: A New Test Approach Towards DPPB
B
Baert, Rogier	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Balasubramanian, Keshav	Resiliency of automotive detection networks on GPU architectures
Becker, Bernd	Security Compliance Analysis of Reconfigurable Scan Networks
Bhaskaran, Bonita	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Bidmeshki, Mohammad-Mahdi	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
Blanton, Shawn	Characterization of Locked Combinational Circuits via ATPG Improving Test Chip Design Efficiency via Machine Learning
Bramley, Richard	Resiliency of automotive detection networks on GPU architectures
Bryant, Troy	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
C
Caicedo, Jhon	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Cardoso Medeiros, Guilherme	Device-Aware Testing: A New Test Approach Towards DPPB
Carter-Brown, Christina	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug
Chakrabarty, Krishnendu	Hardware Fault Tolerance for Binary RRAM Crossbars Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Chakrabarty, Krishnendu	Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network Structural and Functional Test Methods for Digital Acoustofluidic Biochips
Chakravadhanula, Krishna	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Chao, Mango	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Chatterjee, Abhijit	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Chaudhuri, Arjun	Hardware Fault Tolerance for Binary RRAM Crossbars
Chehab, Bilal	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Chen, Hao	IPP: High Quality Test Methodology for Highly Reliable Devices
Chen, Po-Lin	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Chen, Ying-Yen	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Chen, Yiran	Hardware Fault Tolerance for Binary RRAM Crossbars
Cheng, Ken Chau-Cheung	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Chern, Mason	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Chickermane, Vivek	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Chou, Leon	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Chowdhury, Sreeja	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
Colburn, Jonathon E.	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Colle, Frederik	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Coyette, Anthony	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
D
Damljanovic, Aleksa	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
De Luca, Sergio	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Dobbelaere, Wim	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Duvalsaint, Danielle	Characterization of Locked Combinational Circuits via ATPG
F
Fang, Chenlei	Improving Test Chip Design Efficiency via Machine Learning
Ferguson, Ryan	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Fieback, Moritz	Device-Aware Testing: A New Test Approach Towards DPPB
Floridia, Andrea	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Forte, Domenic	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
Foutz, Brian	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
G
Ganji, Fatemeh	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
Gao, Zhan	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Gielen, Georges	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Goossens, Kees	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Goteti, Prashant	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Grupp, Richard	IPP: Applications of Hierarchical Test
Gu, Xinli	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Gummidipoondi Jayasankaran, Nithyashankari	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Gupta, Sandeep	Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic
Gupta, Sanya	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
H
Hamdioui, Said	Device-Aware Testing: A New Test Approach Towards DPPB
He, Chen	IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers
He, Yi	Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
Hellebrand, Sybille	A Hybrid Space Compactor for Adaptive X-Handling
Hess, Kevin	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug
Hill, Michael J	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Holst, Stefan	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Hsu, Charles C.-H.	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Hu, Jiang	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Hu, Min-Chun	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Huang, Andrew Yi-Ann	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Huang, Qicheng	Improving Test Chip Design Efficiency via Machine Learning
Huang, Tony	Structural and Functional Test Methods for Digital Acoustofluidic Biochips
Huang, Yanxiang	Resiliency of automotive detection networks on GPU architectures
Huisken, Jos	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Hukerikar, Saurabh	Resiliency of automotive detection networks on GPU architectures
I
Ichiyama, Kiyotaka	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
Ikeda, Kosuke	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Ishida, Masahiro	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
J
Jayakumar, Greeshma	IPP: Applications of Hierarchical Test
Jiang, Xu-Hao	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Jutman, Artur	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
K
Kao, Shu-Yi	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Karri, Ramesh	Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
Keezer, David	A Framework for Design of Self-Repairing Digital Systems
Keller, Brion	IPP: Applications of Hierarchical Test
Kim, Jisuk	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
Kimura, Takashi	A New Test Method for the Testing Large Current Magnetic Sensors
Kiyokawa, Toshiyuki	A New Test Method for the Testing Large Current Magnetic Sensors
Knoth, Rob	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
Kochte, Michael A.	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Kogan, Tal	IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Krishnamoorthy, Arun	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Kumisbek, Gani	IEEE Std. P1687.1: translator and protocol
Kusaka, Takashi	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
L
Lakshmipathy, Madhu Sudhan	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Larsson, Erik	IEEE Std. P1687.1: translator and protocol
Lee, Chen-Shiun	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Lee, Dong-Zhen	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Lee, Jih-Nung	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Lee, Jinyub	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
Leventhal, Ira	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Li, Katherine Shu-Min	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Li, Xin	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Li, Yanjing	Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
Liang, Aaron C.-W.	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Liang, Tung-Che	Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
Liu, Mengyun	Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Liu, Yingdi	Test Time and Area Optimized BIST Scheme for Automotive ICs
Liu, Zeye	Improving Test Chip Design Efficiency via Machine Learning
Lotfi, Atieh	Resiliency of automotive detection networks on GPU architectures
Lylina, Natalia	Security Compliance Analysis of Reconfigurable Scan Networks
M
Maaz, Mohammad Urf	A Hybrid Space Compactor for Adaptive X-Handling
Maghari, Nima	Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
Makala, Sarath	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Makris, Yiorgos	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Malagi, Santosh	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Marinissen, Erik Jan	Device-Aware Testing: A New Test Approach Towards DPPB IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Martorana, Rosario	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Mayer, Jeff	Test Time and Area Optimized BIST Scheme for Automotive ICs
Mclaurin, Teresa	IPP: The Challenges of Implementing an MBIST Interface: A Practical Application
Moghaddam, Elham	Test Time and Area Optimized BIST Scheme for Automotive ICs
Mozaffari, Seyed Nima	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Mukherjee, Nilanjan	Test Time and Area Optimized BIST Scheme for Automotive ICs
Murali, Prathamesh	IEEE Std. P1687.1: translator and protocol
N
Nakamura, Shigeo	A New Test Method for the Testing Large Current Magnetic Sensors
Narayanun, Kaushik	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Natarajan, Suriyaprakash	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Neethirajan, Deepika	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Nien, Yu-Teng	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
O
Ockunzzi, Kelly	IPP: Applications of Hierarchical Test
Omuro, Toshiyuki	A New Test Method for the Testing Large Current Magnetic Sensors
P
Pagalone, Vinod	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Pai, Sreekanth	IPP: Applications of Hierarchical Test
Pandey, Sujay	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Papameletis, Christos	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Piumatti, Davide	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
Pomeranz, Irith	Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
Portolan, Michele	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
R
Racunas, Paul	Resiliency of automotive detection networks on GPU architectures
Raiola, Pascal	Security Compliance Analysis of Reconfigurable Scan Networks
Rajavendra Reddy, Gaurav	VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
Rajendran, Jeyavijayan	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Rajski, Janusz	Test Time and Area Optimized BIST Scheme for Automotive ICs
Rao, Siddharth	Device-Aware Testing: A New Test Approach Towards DPPB
Rojas, Luis D.	IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug
Ruospo, Annachiara	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
S
Sanabria Borbon, Adriana	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Sanchez, Ernesto	A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Sapati, Mahendar	Test Time and Area Optimized BIST Scheme for Automotive ICs
Sarangi, Shantanu	An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Sauer, Matthias	Security Compliance Analysis of Reconfigurable Scan Networks
Saxena, Nirmal	Resiliency of automotive detection networks on GPU architectures
Schaub, Keith	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Schneider, Eric	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Schrom, Gerhard	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
Shan, Chuanhe	Deploying A Machine Learning Solution As A Surrogate
Shen, Cheng-Hsien	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Singh, Adit	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
Singhal, Sarthak	IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Sinha, Arani	Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology
Solecki, Jedrzej	Test Time and Area Optimized BIST Scheme for Automotive ICs
Sprenger, Alexander	A Hybrid Space Compactor for Adaptive X-Handling
Squillero, Giovanni	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Su, Fei	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Sumikawa, Nikolas	Deploying A Machine Learning Solution As A Surrogate
Sunter, Stephen	Efficient Analog Defect Simulation
Swenton, Joseph	IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Sánchez-Sinencio, Edgar	Breaking Analog Locking Techniques via Satisfiability Modulo Theories
T
Taouil, Mottaqiallah	Device-Aware Testing: A New Test Approach Towards DPPB
Taylor, Mark	IPP: Applications of Hierarchical Test
Tille, Daniel	Test Time and Area Optimized BIST Scheme for Automotive ICs
Tsai, Cheng-Yen	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Tsertov, Anton	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Tyszer, Jerzy	Test Time and Area Optimized BIST Scheme for Automotive ICs
V
Vanhooren, Ronny	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Vunnam, Ravi Sankar	IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors
W
Wahba, Ahmed	Deploying A Machine Learning Solution As A Surrogate
Wang, Fangzhou	Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic
Wang, Li-C.	Deploying A Machine Learning Solution As A Surrogate
Wang, Min-Jer	IPP: High Quality Test Methodology for Highly Reliable Devices
Wang, Sying-Jyan	IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
Wen, Charles H.-P.	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
Wen, Xiaoqing	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data
Wu, Kai-Chiang	Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Wu, Lizhou	Device-Aware Testing: A New Test Approach Towards DPPB
Wunderlich, Hans-Joachim	Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data Security Compliance Analysis of Reconfigurable Scan Networks
X
Xama, Nektar	IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Xanthopoulos, Constantinos	IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion
Xu, Zheng	Safety Design of a Weight Stationary Convolutional Neural Network Accelerator
Y
Yan, Bonan	Hardware Fault Tolerance for Binary RRAM Crossbars
Yang, Jingchi	A Framework for Design of Self-Repairing Digital Systems
Yoo, Sungjoo	Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip
Z
Zhang, Min	On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Zhang, Peiran	Structural and Functional Test Methods for Digital Acoustofluidic Biochips
Zhong, Zhanwei	Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network Structural and Functional Test Methods for Digital Acoustofluidic Biochips
Zhu, Haodong	Structural and Functional Test Methods for Digital Acoustofluidic Biochips

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