ABSTRACT. Fully Integrated Voltage Regulators (FIVRs) are switching voltage regulators integrated on to the same die as the CPU and Graphics cores, in 4th and 5th generation Intel® Core(TM) microprocessors. Practical limitations prevent the application of traditional voltage regulator characterization methods to FIVRs. To overcome these challenges, new methods and techniques had to be developed for the testing and characterization of FIVRs. Power Efficiency (η) is one of the key performance metrics of voltage regulators. In this paper we explain the methods used to measure the Power Efficiency of FIVRs. These methods are applicable to Integrated VRs in general and are not specific to FIVRs alone. Description of power loss components and extraction of the loss coefficients from curve fitting technique is also presented. Measured results show that the proposed methods are highly repeatable with worst-case run-to-run variation of 0.4%. The results also show that the worst-case error is <1% when compared to pre-Si simulation results.

ABSTRACT. An MBIST interface can enable very high-quality test, which is required by emerging markets such as autonomous automotive, with much less impact to power, performance and area (PPA) than the traditional method of instantiating an MBIST controller. The MBIST interface is able to achieve the improvement in PPA and higher quality test by reusing functional paths to connect to the memories during test. Automation of creating an MBIST controller that understands this way of accessing the memories requires partnership between EDA and the IP provider. This paper discusses practical aspects of implementing an MBIST interface and a 3rd party MBIST controller.

ABSTRACT. This paper introduces a high quality screening methodology, using Integrated Passive Device (IPD) as an example device, which has the capability to increase power integrity of Integrated Fan Out Wafer Level Chip Scale Package (InFO WLCSP). InFO WLCSP is a more cost effective solution to achieve “More than Moore’s law” for mobile devices than 3D integrated circuits (3DIC). Ultra-thin IPD with high capacitance density is capable to further shrinking InFO package dimensions and boosting its performance. Although the cost percentage of an IPD in the whole InFO package is negligible, a defective IPD can cause the whole InFO package malfunctioned. Traditional test methods such as good die in a bad cluster (GDBC) and dynamic part averaging testing (DPAT) are used screening IPD devices, however it is insufficient for high quality screen standards. In this paper, we pro-pose a novel methodology that leads to an effective screening method to guarantee high quality and reliable IPD devices for InFO packages. We will show results on some industrial cases to validate our claims.

ABSTRACT. Traditionally, spatial failure patterns in wafer defect maps are used for root cause analysis in order to improve defect diagnosis resolution and yield learning. However, the types of recognizable spatial failure patterns are limited, which restricts the achievable diagnosis resolution. Test items executed in the wafer test process provide useful information regarding the root cause of defects to improve yield; however, the challenge is how to exploit such information for diagnosis. In this paper, we explore to use distribution of data collected from various test items to generate a DNA-like wafer defect signature to uniquely identify wafer defects effectively and efficiently. Experimental results show that the proposed TestDNA method is more robust and can identify more defect types than state-of-art failure pattern recognition, which will lead to more accurate diagnosis. The results will be helpful to achieve zero defects in manufacturing, especially life-critical automotive industry.

ABSTRACT. Safety is the most important aspect of an autonomous driving platform. Deep neural networks (DNNs) play an increasingly critical role in localization, perception, and control in these systems. The object detection and classification inference are of particular importance to construct a precise picture of a vehicle's surrounding objects. Graphics Processing Units (GPU) are well-suited to accelerate such DNN-based inference applications since they leverage data and thread-level parallelism in GPU architectures. Understanding the vulnerability of such DNNs to random hardware faults (including transient and permanent faults) in GPU-based systems is essential to meet the safety requirements of auto safety standards such as the ISO 26262, as well as to influence the design of hardware and software-based safety features in current and future generations of GPU architectures and GPU-based automotive platforms. In this paper, we assess the vulnerability of object detection and classification DNNs to permanent and transient faults using fault injection experiments and accelerated neutron beam testing respectively. We also evaluate the effectiveness of chip-level safety mechanisms in GPU architectures, such as ECC and parity, in detecting these random hardware faults. Our studies demonstrate that such object detection networks tend to be vulnerable to random hardware faults, which cause incorrect or mispredicted object detection outcomes. The neutron beam experiments show that existing chip-level protections successfully mitigate all silent data corruption events caused by transient faults. For permanent faults, while ECC and parity are effective in some cases, our results suggest the need for exploring other complementary detection methods, such as periodic online and offline diagnostic testing.

ABSTRACT. Freedom from Interference (FFI) is one of the critical criteria in a mixed-criticality system. In this paper we propose a causal learning approach using field anomaly data mining to address challenges of FFI verification.

ABSTRACT. Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed and analyzed two safety design techniques include Algorithm Based Atomic Error Checking-1 (ABAEC-1) and ABAEC-2 for a Weight Stationary (WS) Convolutional Neural Network (CNN) accelerator focusing on low latency and low overhead error detection and error correction with no performance degradation. The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for online fault management and error recovery. We applied the design techniques on an industry quality CNN accelerator and demonstrated that we could achieve the required Diagnostic Coverage (DC) goal with minimal area and power and runtime error recovery overhead and no functional performance degradation for selected configurations.