ABSTRACT. With today's tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two principal challenges: (1) production test responses are usually highly compacted reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compacted failure data and under process variations. An innovative combination of variation-invariant structural analysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compacted test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.

ABSTRACT. In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify ``more realistic'' faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

ABSTRACT. To ensure the functional safety of autonomous systems, periodic in-system tests must detect evolving hardware problems before they actually cause failures. In this context the test for small delay faults plays an important role, as small delay faults can indicate potential early life failures or wearout problems. However, providing the proper infrastructure for built-in small delay test is a challenging task. Typically a “faster-than-at-speed test” (FAST) with several different frequencies is used to detect also “hidden” small delays which can only be propagated over short paths. But then outputs at the end of long paths may no longer reach their stable values at the observation time and must be considered as unknown (“X”) values. As a consequence, test response compaction for FAST has to cope with high X-rates varying with the test frequencies. State of the art X-handling schemes do not take into account these specific conditions, nevertheless they can provide the basis for a flexible solution as needed for FAST. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals, which can be adapted to varying conditions. It can be effectively tuned to FAST by partitioning the compactor into several smaller blocks and using an appropriate mapping from circuit outputs to compactor inputs. As demonstrated in previous work, the pseudo-random control of stochastic test response compaction can be optimized for high fault efficiency, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on preliminary experimental results indicating that many faults are lost in the compaction of relatively few „critical“ test patterns. Similar as in mixed-mode schemes for test pattern generation, a deterministic compaction phase for these critical patterns is added to the test. In this phase the existing compactor structure is re-used, but controlled by specifically determined deterministic control vectors. As shown by the experimental results, this way the fault efficiency can be increased at little extra cost.

ABSTRACT. A digital microfluidic biochip (DMFB) is an attractive platform for immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in biochemistry. A recent generation of biochips uses a micro-electrode-dot-array (MEDA) architecture, which provides fine-grained controllability of droplets and seamlessly integrates microelectronics and microfluidics using CMOS technology. In order to ensure robust fluidic operations and high confidence in the outcome of biochemical experiments, chip testing, fault diagnosis and fault recovery are critical for MEDA biochips. In this paper, we present an effective fault-recovery solution based on the homogeneous structure of MEDA. Since the microelectrode cell (MCs) in a MEDA biochip are identical, we add multiplexers for reconfigurability, whereby an MC with faulty components can use the hardware resources in a neighboring MC. In addition, we use the IEEE 1687 (a.k.a. IJTAG) network to reduce the number of control signals need for the multiplexers, and to provide flexible sub-scan chain access for the fault-recovery control flow. A comprehensive set of simulation results demonstrates the effectiveness of the proposed fault-recovery solution for MEDA biochips.

ABSTRACT. RSFQ, a Josephson-junction based technology, is becoming attractive due to its low energy and high speed. Researchers have designed cell and built circuits by composing the cells. In addition to simulations, test chips for some designs have been fabricated to verify their functionality. Researchers also developed abstractions and methodologies for characterization of the cells under non-idealities such as process variations and fine tune the cell parameters for maximum operating margin. Implicitly they assume that cells can be connected together to compose a larger circuit. The logic behavior of the large circuit will be the logic composition of the cells and its timing behavior will be determined based on properties of the timing of each individual cell. However, failures are found in larger circuits built using these cells. Therefore, it is important to understand and clarify the abstraction of the cells and come up with more robust designs and a more well-understood cell characterization methodology. In this paper, we propose a multi-cell characterization methodology, where we perform combinatorial study of multi-cell circuits systematically. We perform locally exhaustive simulation and analysis to identify weakness of the cell and the abstraction. Any discrepancies between circuit simulation and logic simulation are used to guide our redesign, such as (1) tuning the parameters of the cell; (2) redesigning the cell; (3) changing the fundamental definitions (e.g., the definition of arrival time of the logic signal); (4) identifying rules for logic synthesis. We demonstrate the effectiveness of our approach by improving the robustness of an existing cell library. We also present results of simulations for large benchmark circuits built using the improved cell library.

ABSTRACT. Resistive random-access memory (RRAM)-based computing systems (RCS) are being advocated for neural network acceleration. The memristor is the unit cell of an RCS and it is susceptible to process variations and manufacturing defects. Therefore, it is essential to tolerate faulty memristors to ensure intended system operation. We present the architecture of a novel processing element to tolerate both stuck-at and undefined-state faults in binary RRAM cells. We also describe a 4T1R reconfigurable cell-based crossbar design with an ancillary 3T mesh to provide 100% hardware fault tolerance for random and clustered fault distributions for up to 50% fault density. The proposed 4T1R cell is 2.04× smaller than the state-of-the-art neuromorphic SRAM cell. Evaluation results for binary pattern-matching and digit recognition applications demonstrate the effectiveness of our fault tolerance methodology.

ABSTRACT. In this paper we present an ATPG-based method to characterize the security of combinational logic locking techniques. Results demonstrate that this method is effective at solving keys in a majority of the logic locking techniques.

ABSTRACT. Reconfigurable scan networks (RSN) support diagnosis but may introduce security risks due to side-channels. This paper analyses the information flow of a system and verifies that no additional channels are introduced by an RSN.

ABSTRACT. As digital microfluidic biochips (DMFBs) make the transition to the marketplace for commercial exploitation, security and intellectual property (IP) protection are emerging as important design considerations. Recent studies have shown that DMFBs are vulnerable to reverse engineering aimed at stealing biomolecular protocols (IP theft). The IP piracy of proprietary protocols may lead to significant losses for pharmaceutical and biotech companies. The micro-electrode-dot-array (MEDA) is a next-generation DMFB platform that supports real-time sensing of droplets and has the added advantage of important security protections. However, real-time sensing offers opportunities to an attacker to steal the biochemical IP. We show that the daisychaining of microelectrodes and the use of one-time-programmability in MEDA biochips provides effective bitstream scrambling of biochemical protocols. To examine the strength of this solution, we develop a SAT attack that can unscramble the bitstreams through repeated observations of bioassays executed on the MEDA platform. Based on insights gained from the SAT attack, we propose an advanced defense against IP theft. Simulation results using real-life biomolecular protocols confirm that while the SAT attack is effective for simple instances, our advanced defense can thwart it for realistic MEDA biochips and real-life protocols.

ABSTRACT. A scalable framework for the design of self-testable, self-correcting, and self-repairing digital systems is presented. Modular redundancy, distributed bit-error-rate measurement, and autonomous reconfiguration ensures error-free operation even during self-repair. A case-study demonstrates the effectiveness.

ABSTRACT. This paper proposes a supervised learning method to predict system-level power supply noise during scan tests using silicon measurements. Our approach is significantly faster than conventional estimation methods and can potentially reduce the test time.

ABSTRACT. This paper proposes a machine learning-based method for automatic generation of electronic fuse configuration which is based on the variational autoencoder and genetic algorithm. We evaluated the proposed method with Samsung 64-stacked VNAND chips.

ABSTRACT. Resilience to soft errors is essential for ensuring the robust-ness of a computing system. In this paper, we present anew soft error resilience approach called TSSER (time-sliced soft error resilience), which enables resilience features for instructions that are most likely to cause errors only to minimize system-level energy costs while achieving high levels of resilience. Our TSSER idea (1) takes advantage of the observation that protecting a fraction of instructions in an application already achieves most of the resilience benefits,(2) utilizes circuit-level features that allow resilience mode to be turned on/off, and (3) bridges the gap between application knowledge and circuit features by devising novel ISA and microarchitectural techniques to achieve optimized tradeoffs.Our results obtained from RTL implementation and detailed simulation show that, for various applications from the SPEC and PARSEC benchmark suites, TSSER achieves 65X reduction in SDC rate (a common metric to measure soft error resilience) while imposing 16.8% (11.3%) processor-level energy cost for in-order (out-of-order) processors. This is a significant improvement compared to existing techniques that impose 32%-81% (18%-83%) energy overhead. Our technique also enables flexible tradeoffs between SDC rate and system cost.

ABSTRACT. Traditional low cost scan based structural tests no longer suffice for delivering acceptable defect levels in many processor SOCs, especially those targeting low power applications. Expensive functional system level tests (SLTs) have become an additional and necessary final test screen. Efforts to eliminate or minimize the use of SLTs have focused on new fault models and improved test generation methods to improve the effectiveness of scan tests. In this paper we argue that given the limitations of scan timing tests, such an approach may not be sufficient to detect all the low voltage failures caused by circuit timing variability that appear to dominate SLT fallout. Instead, we propose an alternate approach for meaningful cost savings that adaptively avoids SLT tests for a subset of the manufactured parts. This is achieved by using parametric and scan tests results from earlier in the test flow to identify low delay variability parts that can avoid SLT with minimal impact on DPPM. Extensive SPICE simulations support the viability of our proposed approach. We also show that such an adaptive test flow is also very well suited to real time optimization during the using machine-learning techniques.

ABSTRACT. A fundamental part of the new IEEE Std 1687 is the Instrument Connectivity Language (ICL), which allows for an abstract description of the scan network. The big novelty if compared to legacy solutions like BSDL is the possibility of describing new topology-enabling elements such as the ScanMuxes in a behavioural way which can be easily and efficiently exploited by Test Generation Tools to retarget instrument-level operations to top-level patterns. This means that for a given design, the Developer will have to write both the RTL and the ICL descriptions: to the author’s best knowledge there is no automated tool to make the translation RTL to ICL. This methodology is error-prone due to the human factor, the difference in intent in the two descriptions and the syntactic and semantic complexity of the languages. Incoherence between ICL and RTL will result in retargeting errors, so it is fundamental to validate the equivalence between the two descriptions. This paper presents an automated methodology that starting from the ICL description is able to generate a set of RTL testbenches that can be simulated against the original RTL model to detect discrepancies and incoherence, and provides quantitative metrics in terms of code and functional coverage. Experimental results are reported on the set of ITC2016 set of benchmark networks.

ABSTRACT. A digital microfluidic biochip (DMB) is an attractive platform for automating laboratory procedures in microbiology. However, a major problem associated with today's DMBs is the risk of cross-contamination due to undesirable fouling of the electrode surface. To overcome the above problem, a contactless liquid-handling biochip technology referred to as acoustofluidics has recently been proposed, and droplet manipulations on acoustofluidic biochips have also been experimentally demonstrated. In order to ensure robust fluidic operations and high confidence in the outcome of biochemical experiments, acoustofluidic biochips must be adequately tested before they are used for bioassay execution. This paper presents the first approach for testing of an acoustofluidic biochip that includes an array of interdigital transducers (IDTs). We first present structural test techniques to evaluate the pass/fail status of each IDT, and identify the type of fault if it fails. In order to ensure correct operation of functional units, e.g., mixers and routers, we also present functional test techniques to address fundamental acoustofluidic operations such as droplet transportation and droplet mixing. We evaluate the proposed test methods using experiments on fabricated acoustofluidic biochips.

ABSTRACT. When logic redundancy results in undetectable target faults, gate-exhaustive faults provide extra coverage for sites where coverage is missing. The gate-exhaustive approach is applied selectively to avoid considering large numbers of faults.

ABSTRACT. In recent high-speed data transmissions, a multi-level signaling such as a pulse amplitude modulation (PAM) is adopted instead of binary signaling to enable higher data rate. For testing PAM receivers, stressed testing which utilizes test signal with jitter and noise is very important. This paper introduces a jitter injection module for 4-level PAM (PAM4) signals. It can generate a 52-Gbps PAM4 signal from two 26-Gbps non-return-to-zero (NRZ) signals and inject jitter with frequency up to 1 GHz and amplitude up to 100 ps into the PAM4 signal. Experimental results demonstrate injecting of sinusoidal jitter, random jitter and bounded uncorrelated jitter into PAM4 signals.

ABSTRACT. This work proposes an SMT-based attack technique to evaluate the resilience offered by the existing analog defense schemes against the supply chain attacks. The attack results on different locked analog circuits are demonstrated.

ABSTRACT. Counterfeit electronics impact the global economy and pose life-threatening risks to critical systems and infrastructure. Analog/mixed-signal (AMS) chips are the most widely reported counterfeit chip type, but existing countermeasures are impractical for detecting them. In this paper, we propose a method to detect recycled AMS counterfeits that exploits degradation of power supply rejection ratio (PSRR) in low drop out (LDO) regulators. Our zero cost approach does not require information about the component's design. Moreover, due to the ubiquity of LDOs, it may apply to active and legacy AMS system on chips (SoCs). To evaluate the feasibility and effectiveness of our method, we use an automated test setup to collect PSRR data from commercial off-the-shelf LDOs before and after aging. Machine learning algorithms ranging from unsupervised to supervised are applied to differentiate between aged (i.e., synthetically recycled) and new LDOs. Silicon results confirm that semi-supervised and supervised algorithms are effective even with LDOs used less than 10 days.

ABSTRACT. This paper addresses inherent inefficiencies in measuring a test’s defect coverage of industrial mixed-signal ICs: unclear criteria for what comprises a care-about defect, long simulation time per defect, and identifying corrective action for undetected defects.

ABSTRACT. As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimising test time and area overhead during in-system test ap-plications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops between control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs confirm feasibility of the proposed BIST scheme and are reported herein.

ABSTRACT. This work presents a decentralized software scheduler for the concurrent execution of in-field Software Test Libraries in multi-core scenarios. The effectiveness was experimentally evaluated on an industrial automotive multi-core System-on-Chip manufactured by STMicroelectronics.

ABSTRACT. A novel method is proposed for adjustment and inspection of large current sensors, which eliminates various difficulties arising from the very high currents required. Evaluation results for the proposed the test system are also discussed.

ABSTRACT. Hierarchical test is a new partitioned-test method designed to ease computing resources and run times required for automatic test pattern generation (ATPG) on very large designs. This paper discusses the general architecture of hierarchical test. Details of our implementation, including improved parallel testing of identical logic blocks, are described. Results from three production designs, presented as a case study, show the benefits of using hierarchical test on very large designs.

ABSTRACT. In the emerging era of large scale SoCs comprised from complex IPs, typically designed for AI and Automotive applications, it is essential to embrace an innovative approach to overcome DFT challenges. One of these challenges is to provide a fast time to market solution. This solution must be generic, scalable, robust and Functional Safety (FuSa) aware.

To accomplish this challenge, a generic Virtual Memory Wrapper (VMW) and a Virtual Memory Container (VMC) are introduced. These structures provide highly parametrized and scalable design, accompanied by a push-button memory BIST insertion flow. This innovative approach allows full decoupling between Functional & Test design aspects of a complex SoC.

ABSTRACT. In this contribution, a machine learning based algorithm to classify system level test failures is proposed. A system level test failure is first modeled as a point in a multi-dimensional feature space. Then, such failure is classified into a pre-determined failure class, using the multi-class Support Vector Machine classifier, via the one-versus-one approach. When the proposed algorithm is automatically applied to a population of failing system level test failures, defect part per million failure trends can be produced, and used to prioritize debug activities. The proposed algorithm was successfully implemented in the latest Intel(R) Xeon(R) 14nm product line, with a classification accuracy of 80% and an average classification time of 20 seconds.

ABSTRACT. Automated defect inspection in manufacturing of microscopic probes is an important task and often requires machine learning driven solutions. A supervised only approach can be challenging, because production manufacturing processes typically have few defects, thus large amounts of labeled training data are generally not available. In this work, we instead employed multiple models in a three-step process, two supervised on the front-end, followed by unsupervised on the back-end to perform one-class unsupervised learning on defect-free images. This paper focuses on the latter unsupervised step where we trained a deep convolutional neural network to complete images where specific regions are cut out. Since the network is trained exclusively on defect-free images, it completes the missing patch with a defect-free replica of the missing image region. The reconstruction error within the cut out region acts an anomaly image which can be used for anomaly detection.

ABSTRACT. Using wafer image classification as an example, this paper discusses the challenges for deploying a machine learning solution as a service and presents methods to overcome the challenges.

ABSTRACT. This work describes a design methodology that deploys a random forest classification technique to predict synthesis outcomes for test chip design exploration. Experiments on creating five full-flow logic test chips, which mimic five different designs, demonstrate the efficacy of the proposed methodology.

ABSTRACT. Contemporary technology nodes exhibit high defectivity due to complex interactions between the process and certain layout topologies/patterns. Foundries identify such patterns during diagnosis, Scanning Electron Microscope (SEM) inspections, Failure Analysis (FA), etc., and create a database to restrict their presence in future designs. However, such a database can be generated only after fabricating a few products, hence making this process reactive. Ideally, foundries would prefer to have a proactive approach, where such sensitive patterns are available up-front during technology development. Thereby, they can build accurate Hotspot Detection models and offer a robust Product Design Kit (PDK) to even the earliest of customers, either by ensuring that the process is immune to such patterns or by including them in the Design For Manufacturability Guidelines (DFMGs). To enable this, Early Design Space Exploration (EDSE) can be performed, wherein an Electronic Design Automation (EDA) tool generates synthetic layout patterns. In this work, we introduce VIPER, a novel method which not only generates realistic and Design Rule-clean layout patterns, but which also offers versatility so that the generated patterns can be intuitively customized to specific needs. We ensure that the generated patterns are representative of real designs by data-mining and learning some of their typical characteristics from designs in previous technology nodes. Effectiveness of the proposed method is contrasted against the state-of-the-art, commercially available EDA tool.