Days: Monday, November 11th Tuesday, November 12th Wednesday, November 13th Thursday, November 14th

Monday, November 11th

View this program: with abstractssession overviewtalk overview

Tuesday, November 12th

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14:00-15:00 Session Global: Global Forum Opening

Global Forum is a special show with the 50th-year ITC.

15:00-16:30 Session w1: Paper 1.#: Defect and Failure Characterization
Location: Washington 1
Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology (abstract)
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging (abstract)
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation (abstract)
15:00-16:30 Session w2: Paper 2.#: System and Memory Test
Location: Washington 2
Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation (abstract)
Device-Aware Testing: A New Test Approach Towards DPPB (abstract)
IEEE Std. P1687.1: translator and protocol (abstract)
15:00-16:30 Session w5: TTTC PhD.#: TTTC PhD Thesis Competition

ETS Winner:

Reliability Modeling and Mitigation for Embedded Memories
Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui
Delft University of Technology, the Netherlands &
Pieter Weckx, Francky Catthoor
Belgium and Katholieke Universiteit Leuven, ESAT, Belgium

ATS Winner:

VTS Winner:

Built-in self-test and self-calibration for analog and mixed signal circuits
Tao Chen, Degang Chen (advisor)
Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

Location: Washington 5
17:00-18:30 Session w1: IPP 1.#: Industrial Practice Papers
Location: Washington 1
IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications (abstract)
IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers (abstract)
IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs (abstract)
IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library (abstract)
17:00-18:30 Session w4: Sky Talks: Sky Talks

Each Sky Talk is 30-minute long.

1. Rob Aitken, Fellow, ARM

2. Praveen Chawla, CTO and President, Edaptive Computing, Inc.

3. Praveen Parigna, TBD

Location: Washington 4
17:00-18:30 Session w5: ITC-Asia.#: ITC-Asia 2019 - Top 3 Papers

1. Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques
Stephan Eggersglüß (Mentor Germany) E-mail: Stephan Eggersglüß

2. Online Testing of Clock Delay Faults in a Clock Network
Chu Wei and Shi-Yu Huang (National Tsing Hua University) E-mail: Chu Wei Shi-Yu Huang

3. An On-chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips
Ahmed Ibrahim and Hans Kerkhoff (University of Twente) E-mail: Ahmed Ibrahim Hans Kerkhoff

Location: Washington 5
Wednesday, November 13th

View this program: with abstractssession overviewtalk overview

08:30-10:00 Session w1: Paper 3.#: Delay Test
Location: Washington 1
Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data (abstract)
Methodology of Generating Timing-Slack-Based Cell-Aware Tests (abstract)
A Hybrid Space Compactor for Adaptive X-Handling (abstract)
08:30-10:00 Session w2: Paper 4.#: Emerging Technologies
Location: Washington 2
Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network (abstract)
Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic (abstract)
Hardware Fault Tolerance for Binary RRAM Crossbars (abstract)
08:30-10:00 Session w3: Paper 5.#: Scan Security
Location: Washington 3
Security Compliance Analysis of Reconfigurable Scan Networks (abstract)
Characterization of Locked Combinational Circuits via ATPG (abstract)
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips (abstract)
08:30-10:00 Session w4: Perspectives: Perspective Of Each 25-Year Period Of ITC

1. First 25 years (1969-1994)

2. Second 25 years (1995-2019)

3. Future 25 years (2020-2044)

Location: Washington 4
08:30-10:00 Session w5: Paper 6.#: AI Track - Regular Papers
Location: Washington 5
A Framework for Design of Self-Repairing Digital Systems (abstract)
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test (abstract)
Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip (abstract)
11:30-13:30 Session Poster

(posters are ordered by their submission #)

[9] Vinayaka Lg (Tessolve Semiconductor Pvt Ltd) and Prashanth Kudva (Tessolve Semiconductor Pvt Ltd). Challenges in Industrializing high integration devices (CPU/FPGA) that has very large digital test content with EOL exceeding 25 years.

[13] Lawrence Luce (Teradyne, Inc.). A Comparsion of ML Categorization Techniques for Test Datalogs.

[16] Kevin Fan (Advantest). High Speed RFADC/RFDAC Test Challenges for ATE.

[21] Steve Huang (Teradyne Taiwan), Ci Kuo (Teradyne Taiwan), Cheng-Cheng Chen (Teradyne Taiwan) and Stockton Chiang (Teradyne Taiwan). UltraFlex AI chip final test design and challenge: A case study.

[23] Saumil Gogri (Texas A&M University), Dr. Jiang Hu (Texas A&M University), Dr. Aakash Tyagi (Texas A&M University), Mike Quinn (Texas A&M University), Swati Ramachandran (Texas A&M University), Fazia Batool (Texas A&M University) and Amrutha Shikaripura (Texas A&M University). A Study on Machine Learning-Guided Stimulus Generation for Functional Verification.

[25] Peter Wohl (Synopsys), John Waicukauski (Synopsys) and Frederic Neuveux (Synopsys). PS-XLBIST: Per-Shift X-Tolerant Logic BIST.

[31] Cheng-Hung Wu (National Cheng Kung University), Yu Huang (Mentor, A Siemens Business), Kuen-Jong Lee (National Cheng Kung University), Wu-Tung Cheng (Mentor, A Siemens Business), Gaurav Veda (Mentor, A Siemens Business), Sudhakar Reddy (Univ. of Iowa), Chun-Cheng Hu (National Cheng Kung University) and Chong-Siao Ye (National Cheng Kung University). Deep Learning Based Test Compression Analyzer.

[33] Shinobu Okanishi (Renesas Electronics Corporation), Kazuki Shigeta (Renesas Electronics Corporation), Satoshi Tanaka (Renesas Engineering Sevices Corporation), Hiroyuki Osawa (Spandnix Inc.), Ric Dokken (Roguevation, Inc.) and Hiroshi Yanagita (Renesas Electronics Corporation). A novel PRPG streaming scan test optimized for failure analysis of field returns.

[34] Robert Redburn (IBM), Sameer Chillarige (Cadence), Nicholai L'Esperance (IBM), Jeff Zimmerman (IBM), Adisun Wheelock (IBM), Anil Malik (Cadence), Martin Amodeo (Cadence), Atul Chhabra (Cadence) and Bharath Nandakumar (Cadence). Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology.

[38] Hui King Lau (Graphcore), Jon Ferguson (Graphcore), Evan Griffiths (Graphcore), Rahul Singhal (Mentor, A Siemens Business) and Lee Harrison (Mentor, A Siemens Business). Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study.

[52] Praveen Raghuraman (Qualcomm India Private Limited), Vaishnavi Sundaralingam (QUALCOMM India Private Limited) and Bharath Vojjala (QUALCOMM India Private Limited). Overcoming Challenges in Maximizing Yield with Memory Repair.

[61] Liyang Lai (Shantou University), Qiting Zhang (Shantou University), Hans Tsai (Mentor, a Siemens Business) and Wu-Tung Cheng (Mentor, a Siemens Business). On Scalable GPU-based Parallel Logic Simulation.

[72] Jan Burchard (Mentor, a Siemens Business), Reinhard Meier (Mentor, a Siemens Business) and Stephan Eggersglüß (Mentor, a Siemens Business). Performance Analysis and Optimization of Reconfigurable Scan Network Architectures.

[94] Govind Radhakrishnan (University of Waterloo), Youngki Yoon (University of Waterloo) and Manoj Sachdev (University of Waterloo). A DFT Scheme for Fault Monitoring in STT-MRAMs.

[97] Mahmoud Abdalwahab (NXP Semiconductors), Tom Waayers (NXP semiconductors) and Willy Slendebroek (NXP semiconductors). Enhanced Limited Pin Test for Analog: “Towards IEEE1687 for Analog”.

[113] Derek Wright (University of Waterloo), Manoj Sachdev (University of Waterloo) and Dhruv Patel (University of Toronto). Sense Amplifier Offset and Weak Cell Test Considerations for Low-Voltage SRAMs.

[115] Tm Mak (ATE Solutions Inc), Neil Jacobson (ATE Solutions Inc) and Louis Ungar (ATE Solutions, Inc.). Utilizing FPGA as Synthetic Instruments for Test Reuse.

[119] Ashish Vanjari (Texas Instruments), Bharat Rajaram (Texas Instruments) and Salvatore Pezzino (Texas Instruments). Framework for Efficient Softwarre Test Library Development for Embedded Core with ASIL-B/SIL-2 Target.

[127] Sreejit Chakravarty (Intel), E Brazil (Intel), Rakesh Kandula (Intel), Neel Shah (Intel), V. R. Sarath (Intel), Rajeev Katta (Intel), A Karthika (Intel) and Veeresha Bevinamatti (Intel). Anatomy of an in-die tester to improve Safety, Infant Mortality and System Availability.

[128] Sreejit Chakravarty (Intel), Fei Su (Intel), Indira A Gohad (Intel), Sudheer B Bandana (Intel), B S Adithya (Intel) and Wei-Ming Lim (Intel). Internal I/O Testing: Definition, Solution and a Case Study .

[142] Tudor Secasiu (Intel), Nancy Wang-Lee (Intel) and Jihad Abbas (Intel). Industrial Practices – Short Paper: Dynamic Temperature Range test and validation strategy for embedded designs and IP blocks.

[154] Michael Laisne (Dialog Semiconductor). Novel IEEE 1687-Like Architectures.

[158] Makoto Eiki (Sony), Keith Schaub (Advantest America), Ira Leventhal (Advantest America) and Brian Buras (Advantest America). In Test Flow Neural Network Inference on the V93000 SmarTest Test Cell Controller.

[159] Jan Schat (NXP Semiconductors), Robert Jin (NXP Semiconductors), Lei Ma (NXP Semiconductors) and Andres Barrilado (NXP Semiconductors). DfT and Functional Safety - often friends, but sometimes rivals.

[161] Jan Schat (NXP Semiconductors), Heiko Ehrenberg (Goepel Electronics), Bradford van Treuren (Consultant) and Ian McIntosh (Leonardo MW Ltd). IEEE P2654 System Test Access Management.

[162] Douglas Sprague (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)), Howard Druckerman (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)) and Chris Le Coz (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)). Custom Point Tooling for ASIC DFT Structural Checking & Test Deliverables.

[163] Chen He (NXP Semiconductor) and Yanyao Yu (NXP Semiconductor). Wafer Level Stress – Enabling Zero Defect for Automotive Microcontrollers without Package Burn-In.

[164] Anıl Özdemirli (Yeditepe University), Ali Arda Yıldız (Mikroelektronik Ltd.) and Uğur Çilingiroğlu (Yeditepe University). Photovoltaic-Powered Contactless Scribe-Line Testing with VLC Downlink and IR-UWB Uplink.

[165] Haiying Ma (Enflame Technology), Rui Guo (Enflame Technology), Quan Jing (Enflame Technology), Jing Han (Enflame Technology), Yu Huang (Mentor - A Siemens Business), Rahul Singhal (Mentor - A Siemens Business) and Wu Yang (Mentor - A Siemens Business). Case Study on Test Strategy of an AI SoC.

[166] Reju Radhakrishnan (Broadcom Inc), Alok Kashyap (Broadcom Inc), Satish Panigatti (Broadcom Inc), Yasuji Oyama (Advantes tAmerica Inc) and At Sivaram (Advantest America Inc). CloudTestingTm Service Enables Board Level Post Silicon Debug.

[167] Kisub Lim (Samsung Electronics). New FPGA Firmware for Multi-Para Probe Card Relay.

[168] Kazuhio Iwasaki (Tokyo Metropolitan University). Wire Length as a Function of Fan-Outs .

[169] Ahreum Lee (Sungkyunkwan University) and Taesup Moon (Sungkyunkwan University). Test item reduction using machine learning in RF semiconductor production.

[170] Spencer Millican (Auburn University), Yang Sun (Auburn University), Soham Roy (Auburn University) and Vishwani Agrawal (Auburn University). Applying Artificial Neural Networks to Test-point Insertion: Delay Fault Coverage and Training Circuit Generation.

[171] Jeongmi Kwon (Mentor Graphics), Ron Press (Mentor Graphics), Dongkwan Han (Samsung Electronics) and Juhee Han (Samsung Electronics). Hierarchical DFT Flow mixed with a Traditional DFT Flow.

[172] Dongkwan Han (Samsung Electronics), Yoseop Lim (Samsung Electronics), Benoit Nadeau-Dostie (Mentor, A Siemens Business), Etienne Racine (Mentor, A Siemens Business) and Raghav Mehta (Mentor, A Siemens Business). Optimized Memory BIST solution for testing CAMs.

[173] Chandra Nalage (Broadcom) and Vidya Neerkundar (Mentor A Siemens Business). Efficient Specifications, Implementation & Tracking of IJTAG (IEEE1687) TDRs.

[174] Dongkwan Han (Samsung Electronics), Hyeonuk Son (Samsung Electronics), Etienne Racine (Mentor, a Siemens Business), Raghav Mehta (Mentor, a Siemens Business) and Harshitha Kodali (Mentor, a Siemens Business). High-Performance Memory BIST Solution for Testing HBM DRAMs.

[175] Anthony Lum (Advantest America Inc), Bin Wang (Advantest America Inc), Rohit Waikar (Advantest America Inc) and At Sivaram (Advantest America Inc). High-Volume Consumer Devices Need High-Voltage Test Solution.

[176] Keno Sato (ROHM Semiconductor), Takashi Ishida (ROHM Semiconductor), Toshiyuki Okamoto (ROHM Semiconductor), Tamotsu Ichikawa (ROHM Semiconductor), Haruo Kobayashi (Gunma University), Kazumi Hatayama (Gunma University), Takayuki Nakatani (Gunma University), Anna Kuwana (Gunma University), Jiang-Lin Wei (Gunma University), Nene Kushita (Gunma University), Hirotaka Arai (Gunma University) and Lei Sha (Gunma University). An Effective INL Test Methodology  For Low Sampling Rate and High Resolution Analog-to-Digital Converter.

[177] Gowrishankar Ilankumaran (Tessolve Semiconductors), Srinivasan Chandrasekaran (Tessolve Semiconductor Pvt. Ltd) and Jagadish Chandrasekaran (Tessolve Semiconductor Pvt. Ltd). Adaptive RF DIB Design for Bench and ATE .

[178] Satish Panigatti (Broadcom), Rahul Singhal (Mentor - A Siemens Business), Varun Rajagopal (Mentor - A Siemens Business) and Knut Mellenthin (Mentor - A Siemens Business). Hierarchical Test with TAP based Silicon Defect Screening.

[179] Philemon Daniel (NIT Hamirpur), Aakash Tyagi (NIT Hamirpur), Shaily Singh (NIT Hamirpur), Garima Gill (National), Anshu Singh Gangwar (NIT Hamirpur), Ganesh Bargaje (NIT Hamirpur) and Kaushik Chakrabarti (NIT Hamirpur). On-Chip Test Decompression and Compaction for EDT using Neural Networks.

[180] Jim Johnson (SiliconAid Solutions, Inc.), Alfred Crouch (Amida Technology Solutions, Inc.) and Bill Atwell (SiliconAid Solutions, Inc.). IJTAG (IEEE 1687) Evolution Status.

[181] Stephen Traynor (NXP). Driving Towards Zero Defects in the Next Generation Automotive Markets.

[182] Gianluca Basile (Teradyne) and Chuck Carline (Teradyne). How use of guardband limits effects production quality in automotive segment and at which cost.

[183] Yuqiao Zhang (Auburn University), Pinchen Cui (Auburn University), Ziqi Zhou (Auburn University) and Ujjwal Guin (Auburn University). SAL: Function Search Attack On Logic Locked Circuits.

[184] Michael Dewey (Marvin Test Solutions), David Hu (Marvin Test Solutions) and Dale Johnson (marvin test solutions). Multi-Site DUT to Tester Interfacing for mmWave Devices.

[185] Weili Wang (cisco). Running In-System MBIST by reusing ATE MBIST tests.

[186] Ric Dokken (Roguevation). Direct Application of IEEE 1450.4 Test Flow on ATE.

[187] Yukiya Miura (Tokyo Metropolitan University) and Kouhei Sato (Tokyo Metropolitan University). Characteristics of Ring Oscillators Considering FPGA structure.

15:00-16:30 Session w1: Paper 7.#: Resilience and System Test
Location: Washington 1
Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution (abstract)
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures (abstract)
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL (abstract)
15:00-16:30 Session w2: Paper 8.#: Special Test Methods
Location: Washington 2
Structural and Functional Test Methods for Digital Acoustofluidic Biochips (abstract)
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults (abstract)
A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces (abstract)
15:00-16:30 Session w3: Paper 9.#: Analog Security
Location: Washington 3
Breaking Analog Locking Techniques via Satisfiability Modulo Theories (abstract)
Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation (abstract)
Efficient Analog Defect Simulation (abstract)
15:00-16:30 Session w4: Paper 10.#: Automotive Track - Regular Papers
Location: Washington 4
Test Time and Area Optimized BIST Scheme for Automotive ICs (abstract)
A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips (abstract)
A New Test Method for the Testing Large Current Magnetic Sensors (abstract)
17:00-18:30 Session w3: IPP 2.#: Industrial Practice Papers
Location: Washington 3
IPP: Applications of Hierarchical Test (abstract)
IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs (abstract)
IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug (abstract)
IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion (abstract)
17:00-18:30 Session w5: Paper 11.#: AI Track - Regular Papers
Location: Washington 5
Deploying A Machine Learning Solution As A Surrogate (abstract)
Improving Test Chip Design Efficiency via Machine Learning (abstract)
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration (abstract)
18:30-21:00 Special Award Reception

To celebrate ITC 50th, we will present special awards to acknowledge contributions to ITC over the 50 years. We will also present special paper-based awards to acknowledge ITC authors in the last 25 years (1995-2019).

Thursday, November 14th

View this program: with abstractssession overviewtalk overview

08:30-10:00 Session w1: Invited: Bringing Test Standards to Fruition

Organizer: Jeff Rearick, AMD

1. Heiko Ehrenberg (Goepel) : How IEEE P1687.1 and IEEE P2654 can cooperate to access on-chip instruments during system assembly test

2. Jeff Rearick (AMD) : Using IEEE P1687.2 to describe analog DFT and write analog tests

3. Steve Sunter (Mentor) : Defining Analog Defect Coverage with IEEE P2427, as if your life depends on it


Location: Washington 1
08:30-10:00 Session w3: IPP 3.#: Industrial Practice Papers
Location: Washington 3
IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors (abstract)
IPP: The Challenges of Implementing an MBIST Interface: A Practical Application (abstract)
IPP: High Quality Test Methodology for Highly Reliable Devices (abstract)
IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning (abstract)
08:30-10:00 Session w4: Paper 12.#: Automotive Track - Regular Papers
Location: Washington 4
Resiliency of automotive detection networks on GPU architectures (abstract)
On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach (abstract)
Safety Design of a Weight Stationary Convolutional Neural Network Accelerator (abstract)