Days: Monday, November 11th Tuesday, November 12th Wednesday, November 13th Thursday, November 14th

Monday, November 11th

View this program: with abstractssession overviewtalk overview

17:00-18:30 Session VC Pitch Tank: VC Funding Opportunity - Panel Like Event


For the first time, ITC brings together a number of  venture capitalists (VCs) to listen to innovative ideas and possibly invest. Startup companies, engineers, faculty, and students are invited to pitch ideas to the VCs and seek funds to help raise their company portfolio or start a new company. Join us for this exciting event. 

VC Panelists:

Serge Leef, DARPA   
Jack Kerrigan, Razor's Edge
Andrew McClure, Forgepoint Capital
Andy Bair, Sway Ventures
David Moehring, General Partner VC
Steven Chen, PFP Cyber
Rafic Makki, Abu Dhabi's Mubadala Fund


Tuesday, November 12th

View this program: with abstractssession overviewtalk overview

09:00-10:30 Session Plenary: Plenary, 1st Keynote and 1st Visionary Talk

Opening Session:

ITC General Chair: Yervant Zorian
ITC Program Chair: Mark Tehranipoor



Mike Campbell, Senior VP Of Engineering, Qualcomm


Dr. Aart de Geus, Chairman and co-Chief Executive Officer, Synopsys

For keynote and Visionary, please see ITC site for more information:

13:00-14:00 Session KV2: 2nd Keynote and 2nd Visionary Talk


Serge Leef, Program Manager, DARPA


John Kibarian, President & CEO, PDF Solutions

For keynote and Visionary, please see ITC site for more information:

14:00-15:00 Session Global: Global Forum Opening

Global Forum is a special show with the 50th-year ITC.

For more information, please see ITC web site:

15:00-16:30 Session w1: Paper 1.#: Defect and Failure Characterization
Location: Washington 1
Characterization of Library Cells for Open-Circuit Defect Exposure: A Systematic Methodology (abstract)
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging (abstract)
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation (abstract)
15:00-16:30 Session w2: Paper 2.#: System and Memory Test
Location: Washington 2
Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation (abstract)
Device-Aware Testing: A New Test Approach Towards DPPB (abstract)
IEEE Std. P1687.1: translator and protocol (abstract)
15:00-16:30 Session w3: Security Track: Security Special Session #1: Hot Topics in HW Security

Organizer: Yousef Iskander, Cisco

Moderator: Yousef Iskander, Cisco

1. Title: FPGA Bitstream Security: A Day in the Life
    Adam Duncan,
Indiana University

2. Title: Challenges and opportunities in removing subjectivity in sensitive security testing
    Apostol Vassilev, NIST

3. Title: Is Backside a New Backdoor in Modern SoCs?
    Navid Asadi, UF

Location: Washington 3
15:00-16:30 Session w4: Panel 2: Panel: Perspective on the future of Hardware Security

Title: Perspective on the future of Hardware Security

Moderator: Saverio Fazzari, BAH


Matt Casto, OSD/MINSEC

Brian Dupaix, AFRL

Adam Sherer, Cadence

Sarah Leeper, Draper

Shawn Fetterolf, Synopsys

Mike Borza, Synopsys

Location: Washington 4
15:00-16:30 Session w5: AI Policy: AI Policy Special Session

Moderator/Coordinator: Mina Hanna, Synopsys

Sky Talk: Dr. Lynne Parker, Assistant Director for AI at the White House Office of Science and Technology Policy (OSTP) (30-minite talk)



- Dr.  Henry Kautz (Director of Intelligent Information Systems/Computer and Information Science and Engineering (CISE) Directorate at the NSF

- Dr. Dimitri Kusnezov, Deputy Under Secretary of AI and Technology at U.S. Department Of Energy

- Dr. Chuck Romine (Director of Information Technology Laboratory (ITL) at the National Institute of Standards and Technology

Location: Washington 5
17:00-18:30 Session w1: IPP 1.#: Industrial Practice Papers
Location: Washington 1
IPP: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications (abstract)
IPP: Advanced Burn-In – An Optimized Product Stress and Test Flow for Automotive Microcontrollers (abstract)
IPP: Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs (abstract)
IPP: Application of Cell-Aware Test on an Advanced 3nm Technology Library (abstract)
17:00-18:30 Session w2: Special 1: Special Session #1 - Standards in 50 years

Session Coordinator: Adam Cron (Synposys)

1. "1149.1: A Foundational Force in IEEE Test Standardization", Adam Ley (Asset-Intertech), Adam Cron (Synopsys)

2. "1500: the Common Infrastructure for SOCs", Erik Jan Marinissen (IMEC), Yervant Zorian (Synopsys)

3. "1450: A Family of Test Description Languages" Rohit Kapur (Cadence), Bernd Koenemann, Greg Maston

Location: Washington 2
17:00-18:30 Session w3: Security Track: Security Special Session #2 - CAD for Security

1. Farimah Farahmandi,UF, Title: SoC Security Powered by Rules and Properties

2. Mike Borza, Synopsys, Title: CAD for Security – A Look Ahead for 5 Years and Beyond

3. Jason Oberg, Tortuga Logic, Title: Leveraging Commercial Simulation and Emulation Methodologies for Hardware Security Verification

Location: Washington 3
17:00-18:30 Session w4: Sky Talks: Sky Talks

1. Rob Aitken, Fellow, ARM, Title: Safety, security and resilience – can we test for all three?

2. Praveen Chawla, CTO and President, Edaptive Computing, Inc., Title: Malicious Implant Detection: From Devices to Systems

3. Praveen Vishakantaiah, Title: Testing the future: A Cloudy to Sunny forecast

Location: Washington 4
17:00-18:30 Session w5: ITC-Asia.#: ITC-Asia 2019 - Top 3 Papers

1. Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques
Stephan Eggersglüß ( Mentor, a Siemens Business, Germany) E-mail: Stephan Eggersglüß

2. Online Testing of Clock Delay Faults in a Clock Network
Chu Wei and Shi-Yu Huang (National Tsing Hua University) E-mail: Chu Wei Shi-Yu Huang

3. An On-chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips
Ahmed Ibrahim and Hans Kerkhoff (University of Twente) E-mail: Ahmed Ibrahim Hans Kerkhoff

Location: Washington 5
Wednesday, November 13th

View this program: with abstractssession overviewtalk overview

08:30-10:00 Session w1: Paper 3.#: Delay Test
Location: Washington 1
Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data (abstract)
Methodology of Generating Timing-Slack-Based Cell-Aware Tests (abstract)
A Hybrid Space Compactor for Adaptive X-Handling (abstract)
08:30-10:00 Session w2: Paper 4.#: Emerging Technologies
Location: Washington 2
Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG Network (abstract)
Multi-cell characterization: Develop robust abstraction for Rapid Single Flux Quantum (RSFQ) Logic (abstract)
Hardware Fault Tolerance for Binary RRAM Crossbars (abstract)
08:30-10:00 Session w3: Paper 5.#: Scan Security
Location: Washington 3
Characterization of Locked Combinational Circuits via ATPG (abstract)
Security Compliance Analysis of Reconfigurable Scan Networks (abstract)
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips (abstract)
08:30-10:00 Session w4: Perspectives: Perspective On Each 25-Year Period Of ITC

This section includes three perspective talks, each to cover a perspective for a 25-year period of ITC:

1. First 25 years (1969-1994) by Jacob Abraham, a TTTC Life-Time Achievement Award receipent

2. Second 25 years (1995-2019) by Li-C. Wang and his research team, to provide an analytic-based trend view of ITC papers in this period

3. Future 25 years (2020-2044) by Jennifer Dworak, from the perspective as the Technical Program Chair for ITC 2020

Location: Washington 4
08:30-10:00 Session w5: Paper 6.#: AI Track - Regular Papers
Location: Washington 5
A Framework for Design of Self-Repairing Digital Systems (abstract)
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test (abstract)
Machine Learning-based Automatic Generation of eFuse Configuration in NAND Flash Chip (abstract)
10:30-11:30 Session KV3: 3rd Keynote and 3rd Visionary Talk


Kevork Kechichian, Senior VP of Engineering, NXP


Joseph Sawicki, Executive Vice President, IC EDA, Mentor, a Siemens Business

For keynote and Visionary, please see ITC site for more information:

11:30-13:30 Session Poster

(posters are ordered by their submission #)

[9] Vinayaka Lg (Tessolve Semiconductor Pvt Ltd) and Prashanth Kudva (Tessolve Semiconductor Pvt Ltd). Challenges in Industrializing high integration devices (CPU/FPGA) that has very large digital test content with EOL exceeding 25 years.

[13] Lawrence Luce (Teradyne, Inc.). A Comparsion of ML Categorization Techniques for Test Datalogs.

[16] Kevin Fan (Advantest). High Speed RFADC/RFDAC Test Challenges for ATE.

[21] Steve Huang (Teradyne Taiwan), Ci Kuo (Teradyne Taiwan), Cheng-Cheng Chen (Teradyne Taiwan) and Stockton Chiang (Teradyne Taiwan). UltraFlex AI chip final test design and challenge: A case study.

[23] Saumil Gogri (Texas A&M University), Dr. Jiang Hu (Texas A&M University), Dr. Aakash Tyagi (Texas A&M University), Mike Quinn (Texas A&M University), Swati Ramachandran (Texas A&M University), Fazia Batool (Texas A&M University) and Amrutha Shikaripura (Texas A&M University). A Study on Machine Learning-Guided Stimulus Generation for Functional Verification.

[25] Peter Wohl (Synopsys), John Waicukauski (Synopsys) and Frederic Neuveux (Synopsys). PS-XLBIST: Per-Shift X-Tolerant Logic BIST.

[31] Cheng-Hung Wu (National Cheng Kung University), Yu Huang (Mentor, a Siemens Business), Kuen-Jong Lee (National Cheng Kung University), Wu-Tung Cheng (Mentor, a Siemens Business), Gaurav Veda (Mentor, a Siemens Business), Sudhakar Reddy (Univ. of Iowa), Chun-Cheng Hu (National Cheng Kung University) and Chong-Siao Ye (National Cheng Kung University). Deep Learning Based Test Compression Analyzer.

[33] Shinobu Okanishi (Renesas Electronics Corporation), Kazuki Shigeta (Renesas Electronics Corporation), Satoshi Tanaka (Renesas Engineering Sevices Corporation), Hiroyuki Osawa (Spandnix Inc.), Ric Dokken (Roguevation, Inc.) and Hiroshi Yanagita (Renesas Electronics Corporation). A novel PRPG streaming scan test optimized for failure analysis of field returns.

[34] Robert Redburn (IBM), Sameer Chillarige (Cadence), Nicholai L'Esperance (IBM), Jeff Zimmerman (IBM), Adisun Wheelock (IBM), Anil Malik (Cadence), Martin Amodeo (Cadence), Atul Chhabra (Cadence) and Bharath Nandakumar (Cadence). Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology.

[38] Hui King Lau (Graphcore), Jon Ferguson (Graphcore), Evan Griffiths (Graphcore), Rahul Singhal (Mentor, a Siemens Business) and Lee Harrison (Mentor, a Siemens Business). Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study.

[52] Praveen Raghuraman (Qualcomm India Private Limited), Vaishnavi Sundaralingam (QUALCOMM India Private Limited) and Bharath Vojjala (QUALCOMM India Private Limited). Overcoming Challenges in Maximizing Yield with Memory Repair.

[61] Liyang Lai (Shantou University), Qiting Zhang (Shantou University), Hans Tsai (Mentor, a Siemens Business) and Wu-Tung Cheng (Mentor, a Siemens Business). On Scalable GPU-based Parallel Logic Simulation.

[72] Jan Burchard (Mentor, a Siemens Business), Reinhard Meier (Mentor, a Siemens Business) and Stephan Eggersglüß (Mentor, a Siemens Business). Performance Analysis and Optimization of Reconfigurable Scan Network Architectures.

[94] Govind Radhakrishnan (University of Waterloo), Youngki Yoon (University of Waterloo) and Manoj Sachdev (University of Waterloo). A DFT Scheme for Fault Monitoring in STT-MRAMs.

[97] Mahmoud Abdalwahab (NXP Semiconductors), Tom Waayers (NXP semiconductors) and Willy Slendebroek (NXP semiconductors). Enhanced Limited Pin Test for Analog: “Towards IEEE1687 for Analog”.

[115] Tm Mak (ATE Solutions Inc), Neil Jacobson (ATE Solutions Inc) and Louis Ungar (ATE Solutions, Inc.). Utilizing FPGA as Synthetic Instruments for Test Reuse.

[119] Ashish Vanjari (Texas Instruments), Bharat Rajaram (Texas Instruments) and Salvatore Pezzino (Texas Instruments). Framework for Efficient Softwarre Test Library Development for Embedded Core with ASIL-B/SIL-2 Target.

[127] Sreejit Chakravarty (Intel), E Brazil (Intel), Rakesh Kandula (Intel), Neel Shah (Intel), V. R. Sarath (Intel), Rajeev Katta (Intel), A Karthika (Intel) and Veeresha Bevinamatti (Intel). Anatomy of an in-die tester to improve Safety, Infant Mortality and System Availability.

[128] Sreejit Chakravarty (Intel), Fei Su (Intel), Indira A Gohad (Intel), Sudheer B Bandana (Intel), B S Adithya (Intel) and Wei-Ming Lim (Intel). Internal I/O Testing: Definition, Solution and a Case Study .

[142] Tudor Secasiu (Intel), Nancy Wang-Lee (Intel) and Jihad Abbas (Intel). Industrial Practices – Short Paper: Dynamic Temperature Range test and validation strategy for embedded designs and IP blocks.

[146] Yi Sun (SMU), Hui Jiang (SMU), Lakshmi Ramakrishnan (SMU), Matan Segal (SMU), Jennifer Dworak (SMU), Kundan Nepal (University of St. Thomas), Theodore Manikas (SMU) and Iris Bahar (Brown University). Configurable DFT: A Methodology to Significantly Reduce Switching Activity During Test.

[154] Michael Laisne (Dialog Semiconductor). Novel IEEE 1687-Like Architectures.

[158] Makoto Eiki (Sony), Keith Schaub (Advantest America), Ira Leventhal (Advantest America) and Brian Buras (Advantest America). In Test Flow Neural Network Inference on the V93000 SmarTest Test Cell Controller.

[159] Jan Schat (NXP Semiconductors), Robert Jin (NXP Semiconductors), Lei Ma (NXP Semiconductors) and Andres Barrilado (NXP Semiconductors). DfT and Functional Safety - often friends, but sometimes rivals.

[161] Jan Schat (NXP Semiconductors), Heiko Ehrenberg (Goepel Electronics), Bradford van Treuren (Consultant) and Ian McIntosh (Leonardo MW Ltd). IEEE P2654 System Test Access Management.

[162] Douglas Sprague (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)), Howard Druckerman (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)) and Chris Le Coz (Avera Semiconductor LLC (Wholly Owned Subsidiary of Global Foundries)). Custom Point Tooling for ASIC DFT Structural Checking & Test Deliverables.

[163] Chen He (NXP Semiconductor) and Yanyao Yu (NXP Semiconductor). Wafer Level Stress – Enabling Zero Defect for Automotive Microcontrollers without Package Burn-In.

[164] Anıl Özdemirli (Yeditepe University), Ali Arda Yıldız (Mikroelektronik Ltd.) and Uğur Çilingiroğlu (Yeditepe University). Photovoltaic-Powered Contactless Scribe-Line Testing with VLC Downlink and IR-UWB Uplink.

[165] Haiying Ma (Enflame Technology), Rui Guo (Enflame Technology), Quan Jing (Enflame Technology), Jing Han (Enflame Technology), Yu Huang (Mentor, a Siemens Business), Rahul Singhal (Mentor, a Siemens Business) and Wu Yang (Mentor, a Siemens Business). Case Study on Test Strategy of an AI SoC.

[166] Reju Radhakrishnan (Broadcom Inc), Alok Kashyap (Broadcom Inc), Satish Panigatti (Broadcom Inc), Yasuji Oyama (Advantes tAmerica Inc) and At Sivaram (Advantest America Inc). CloudTestingTm Service Enables Board Level Post Silicon Debug.

[167] Kisub Lim (Samsung Electronics). New FPGA Firmware for Multi-Para Probe Card Relay.

[168] Kazuhio Iwasaki (Tokyo Metropolitan University). Wire Length as a Function of Fan-Outs .

[169] Ahreum Lee (Sungkyunkwan University) and Taesup Moon (Sungkyunkwan University). Test item reduction using machine learning in RF semiconductor production.

[170] Spencer Millican (Auburn University), Yang Sun (Auburn University), Soham Roy (Auburn University) and Vishwani Agrawal (Auburn University). Applying Artificial Neural Networks to Test-point Insertion: Delay Fault Coverage and Training Circuit Generation.

[171] Jeongmi Kwon (Mentor, a Siemens Business), Ron Press (Mentor, a Siemens Business), Dongkwan Han (Samsung Electronics) and Juhee Han (Samsung Electronics). Hierarchical DFT Flow mixed with a Traditional DFT Flow.

[172] Dongkwan Han (Samsung Electronics), Yoseop Lim (Samsung Electronics), Benoit Nadeau-Dostie (Mentor, a Siemens Business), Etienne Racine (Mentor, a Siemens Business) and Raghav Mehta (Mentor, a Siemens Business). Optimized Memory BIST solution for testing CAMs.

[173] Chandra Nalage (Broadcom) and Vidya Neerkundar (Mentor, a Siemens Business). Efficient Specifications, Implementation & Tracking of IJTAG (IEEE1687) TDRs.

[174] Dongkwan Han (Samsung Electronics), Hyeonuk Son (Samsung Electronics), Etienne Racine (Mentor, a Siemens Business), Raghav Mehta (Mentor, a Siemens Business) and Harshitha Kodali (Mentor, a Siemens Business). High-Performance Memory BIST Solution for Testing HBM DRAMs.

[175] Anthony Lum (Advantest America Inc), Bin Wang (Advantest America Inc), Rohit Waikar (Advantest America Inc) and At Sivaram (Advantest America Inc). High-Volume Consumer Devices Need High-Voltage Test Solution.

[176] Keno Sato (ROHM Semiconductor), Takashi Ishida (ROHM Semiconductor), Toshiyuki Okamoto (ROHM Semiconductor), Tamotsu Ichikawa (ROHM Semiconductor), Haruo Kobayashi (Gunma University), Kazumi Hatayama (Gunma University), Takayuki Nakatani (Gunma University), Anna Kuwana (Gunma University), Jiang-Lin Wei (Gunma University), Nene Kushita (Gunma University), Hirotaka Arai (Gunma University) and Lei Sha (Gunma University). An Effective INL Test Methodology  For Low Sampling Rate and High Resolution Analog-to-Digital Converter.

[177] Gowrishankar Ilankumaran (Tessolve Semiconductors), Srinivasan Chandrasekaran (Tessolve Semiconductor Pvt. Ltd) and Jagadish Chandrasekaran (Tessolve Semiconductor Pvt. Ltd). Adaptive RF DIB Design for Bench and ATE .

[178] Satish Panigatti (Broadcom), Rahul Singhal (Mentor, a Siemens Business), Varun Rajagopal (Mentor, a Siemens Business) and Knut Mellenthin (Mentor, a Siemens Business). Hierarchical Test with TAP based Silicon Defect Screening.

[179] Philemon Daniel (NIT Hamirpur), Aakash Tyagi (NIT Hamirpur), Shaily Singh (NIT Hamirpur), Garima Gill (National), Anshu Singh Gangwar (NIT Hamirpur), Ganesh Bargaje (NIT Hamirpur) and Kaushik Chakrabarti (NIT Hamirpur). On-Chip Test Decompression and Compaction for EDT using Neural Networks.

[180] Jim Johnson (SiliconAid Solutions, Inc.), Alfred Crouch (Amida Technology Solutions, Inc.) and Bill Atwell (SiliconAid Solutions, Inc.). IJTAG (IEEE 1687) Evolution Status.

[181] Stephen Traynor (NXP). Driving Towards Zero Defects in the Next Generation Automotive Markets.

[182] Gianluca Basile (Teradyne) and Chuck Carline (Teradyne). How use of guardband limits effects production quality in automotive segment and at which cost.

[183] Yuqiao Zhang (Auburn University), Pinchen Cui (Auburn University), Ziqi Zhou (Auburn University) and Ujjwal Guin (Auburn University). SAL: Function Search Attack On Logic Locked Circuits.

[184] Michael Dewey (Marvin Test Solutions), David Hu (Marvin Test Solutions) and Dale Johnson (marvin test solutions). Multi-Site DUT to Tester Interfacing for mmWave Devices.

[185] Weili Wang (cisco). Running In-System MBIST by reusing ATE MBIST tests.

[186] Ric Dokken (Roguevation). Direct Application of IEEE 1450.4 Test Flow on ATE.

[187] Yukiya Miura (Tokyo Metropolitan University) and Kouhei Sato (Tokyo Metropolitan University). Characteristics of Ring Oscillators Considering FPGA structure.

13:30-14:30 Session KV4: 4th Keynote and 4th Visionary Talk


Leon Stok, Vice President, IBM


Rafic Zein Makki, Head Technologist and Fellow, Mubadala Ventures

Special Talk in AI Track, Titled: Hyperscale Innovation - The role of AI in enabling the enablers

For keynote and Visionary, please see ITC site for more information:

15:00-16:30 Session w1: Paper 7.#: Resilience and System Test
Location: Washington 1
Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution (abstract)
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures (abstract)
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL (abstract)
15:00-16:30 Session w2: Paper 8.#: Special Test Methods
Location: Washington 2
Structural and Functional Test Methods for Digital Acoustofluidic Biochips (abstract)
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults (abstract)
A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces (abstract)
15:00-16:30 Session w3: Paper 9.#: Analog Security
Location: Washington 3
Breaking Analog Locking Techniques via Satisfiability Modulo Theories (abstract)
Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation (abstract)
Efficient Analog Defect Simulation (abstract)
15:00-16:30 Session w4: Paper 10.#: Automotive Track - Regular Papers
Location: Washington 4
Test Time and Area Optimized BIST Scheme for Automotive ICs (abstract)
A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips (abstract)
A New Test Method for the Testing Large Current Magnetic Sensors (abstract)
15:00-16:30 Session w5: TTTC PhD.#: TTTC PhD Thesis Competition

ETS Winner:

Reliability Modeling and Mitigation for Embedded Memories
Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui
Delft University of Technology, the Netherlands &
Pieter Weckx, Francky Catthoor
Belgium and Katholieke Universiteit Leuven, ESAT, Belgium

VTS Winner:

Built-in self-test and self-calibration for analog and mixed signal circuits
Tao Chen, Degang Chen (advisor)
Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

Location: Washington 5
17:00-18:30 Session w1: ITC-India: ITC-India - Top 3 Presentations

Paper #1

Title: Applications of test techniques for improving Silicon to Pre-silicon timing correlation (Best Paper ITC-India 2019)

Authors: Reecha Jajodia, Kevin Zhou, Jaison Kurien, Tezaswi Raja, Manikandan P, Kartik Joshi, Prashant Singh, Vinayak Srinath, Jonathon Colburn and Sarvesh Sharma

Presenter: Jon Colburn, nVidia.


Paper #2

Title: Test cost reduction through increase in multi-site testing with reduced scan-out pins

Authors: Jaidev Shenoy, Kushal Kamal, Kelly Ockunzzi and Virendra Singh

Presenter: Jaidev Shenoy, Globalfoundries


Paper #3

Title: Improved Diagnosis Methodology for Multi-Defect Scenarios in High Compression Scan Based Designs

Authors: Bharath Nandakumar, Sameer Chillarige, Anil Malik, Atul Chhabra, Wilson Pradeep and Prakash Narayanan

Presenter: Wilson Pradeep, TI

Location: Washington 1
17:00-18:30 Session w2: Panel 3: Panel on 3D

Title: 3D Chip Products Are Now Really Taking Off: Is The Test Community Ready For It?

3D-ICs are finally turning into volume products. On the Gartner hype curve, after the technology trigger and the peak of inflated expectations, we seem to have crossed the trough of disillusionment and find ourselves now on the slope of enlightenment, firmly on our way to the plateau of productivity. Is the test community ready for real products in high volumes will require testing? Do we know which additional tests we need? Is the DfT infrastructure ready and sufficiently standardized to be compatible between multiple dies? Can we probe and test partial and complete die stacks? And will the cost of test be affordable? Expert panelists will give their viewpoints.

Rob Knoth – Product Manager – Cadence Design Systems (OR, USA)
Erik Jan Marinissen – Scientific Director – imec (Belgium)

Moderator: Phil Nigh – R&D Test Engineer – Broadcom (CO, USA)


  • Vivek Chickermane – Distinguished Engineer and R&D Director – Cadence Design Systems (NY, USA)
  • Adam Cron – DfT Expert, Chair of IEEE Std P1838 – Synopsys (GA, USA)
  • Sandeep K. Goel – Academician/Department Manager – TSMC (CA, USA)
  • Jeff Arasmith –Senior Product Marketing Manager – Technoprobe (Italy)
Location: Washington 2
17:00-18:30 Session w3: IPP 2.#: Industrial Practice Papers
Location: Washington 3
IPP: Applications of Hierarchical Test (abstract)
IPP: Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs (abstract)
IPP: Effectively Using Machine Learning to Expedite System Level Test Failure Debug (abstract)
IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning based Image Completion (abstract)
17:00-18:30 Session w4: Auto Track: Automotive Panel

Title: Meeting Automotive Quality & Safety Requirements

Moderator/Organizer: Paolo Bernardi, Polito di Torino


Davide Appello, ST Microelectronics
S. Patil, Qualcomm
Riccardo Marriani, NVidia
Yervant Zorian, Synopsys

Location: Washington 4
17:00-18:30 Session w5: Paper 11.#: AI Track - Regular Papers
Location: Washington 5
Deploying A Machine Learning Solution As A Surrogate (abstract)
Improving Test Chip Design Efficiency via Machine Learning (abstract)
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration (abstract)
Thursday, November 14th

View this program: with abstractssession overviewtalk overview

08:30-10:00 Session w1: Special 2: Special Session #2: Bringing Test Standards to Fruition

Organizer: Jeff Rearick, AMD

Moderator: Al Crouch

1. Heiko Ehrenberg (Goepel) : How IEEE P1687.1 and IEEE P2654 can cooperate to access on-chip instruments during system assembly test

2. Jeff Rearick (AMD) : Using IEEE P1687.2 to describe analog DFT and write analog tests

3. Steve Sunter (Mentor, a Siemens Business ) : Defining Analog Defect Coverage with IEEE P2427, as if your life depends on it


Location: Washington 1
08:30-10:00 Session w2: Special 3: Special Session #3: Testing and Fault Tolerance of Emerging Memory-Centric Computing Paradigms

Organizer: Mehdi Tahoori, Karlsruhe Institute of Technology

1. Moritz Fieback, Surya Nagarajan, Mottaqiallah Taouil, and Said Hamdioui, Delft University, Netherlands, Title: Testing Computation-in-Memory Circuits

2. Anteneh Gebregiorgis and Mehdi Tahoori, Karlsruhe Institute of Technology, Germany, Title: Testing of Neuromorphic Circuits: Structural vs Functional

3. Krishnendu Chakrabarty, Duke University, USA, Title: Fault-Tolerant Neuromorphic Computing Systems


Location: Washington 2
08:30-10:00 Session w3: IPP 3.#: Industrial Practice Papers
Location: Washington 3
IPP: Efficiency measurement method for Fully Integrated Voltage Regulators used in 4th and 5th generation Intel® microprocessors (abstract)
IPP: The Challenges of Implementing an MBIST Interface: A Practical Application (abstract)
IPP: High Quality Test Methodology for Highly Reliable Devices (abstract)
IPP: TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning (abstract)
08:30-10:00 Session w4: Paper 12.#: Automotive Track - Regular Papers
Location: Washington 4
Resiliency of automotive detection networks on GPU architectures (abstract)
On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach (abstract)
Safety Design of a Weight Stationary Convolutional Neural Network Accelerator (abstract)
08:30-10:00 Session w5: AI Track: AI Special Session: The New Comers

This last session of the AI track includes two invited talks from the new comers (under age 30) in the test community, followed by a 30-minute brainstorming from the audiences to provide their perspectives to the new comers on AI in Test.

Invited Talks:

1. Apik Zorian, Basim Shanyour, and Milir Vaseekar, Synopsys Inc., Title: Machine Learning-Based DFT Recommendation System for ATPG QOR

2. Jay Shan, IE3A, Inc., Title: Intent-Driven Analytics: To Talk or Not To Talk?

3. Brainstorming (By Audience) - Your Perspective of AI in Test

Location: Washington 5
10:30-11:30 Session KV5: 5th Keynote and 5th Visionary Talk


Giovanni De Micheli, Director IEE Center, EPFL


Greg Smith, President Semiconductor Test, Teradyne

For keynote and Visionary, please see ITC site for more information:

13:00-14:00 Session KV6: 6th Keynote and 6th Visionary Talk


Andreas Aal, Semiconductor Strategy & Reliability, Volkswagen AG


Keith Schaub, Vice President Applied Research and Technology, Advantest

For keynote and Visionary, please see ITC site for more information:

14:30-16:00 Session w2: Special 5: Special Session #5 - HIR

Title: Special Session on Heterogeneous Integration Technology Roadmap (HIR)

Description: This session begins with a Sky Talk to provide an overview of the current state of HIR, followed by a panel discussion.

Moderator: Marc Hutner, Teradyne

Sky Talk: Dr. Bill Bottoms, HIR Chairman, 3MTS


Dave Armstrong, Advantest 

Brady Benware, Mentor, a  Siemens Business

Bill Bottoms, 3MTS

Erik Jan Marinissen, IMEC

Location: Washington 2
14:30-16:00 Session w4: Auto Track: Automotive Special Session: Automotive Safety

Title: Automotive Special Session: Reliability & Safety

Organizer: Yervant Zorian, Synopsys

1. Sky Talk: Vilas Sridharan, Senior Fellow, AMD, Title: From Research to Product: RAS Features in EPYC and Radeon Instinct

2. Invited Talk: G. Boschi, H. Shaheen, D. Luongo, D. Lazzarotti, Intel, H. Grigoryan, G. Harutyunyan , S. Shoukourian, Synopsys.
    Title: Memory FIT Rate Mitigation Technique for Automotive SoCs

3. Invited Talk: Nelly Feldman, Arnaud Sanson (STMicroelectronics), Karen Darbinyan, Arun Kuma (Synopsys). Title: Manufacturing screening and diagnostic flow for advanced technologies automotive system-on-chips


Location: Washington 4