Panel Organizer: Bill Eklow (affiliation unknown)

This panel will explore the mysteries of unknown, unknowns in test. Unknowns are often why we end up solving a wrong problem, taking a wrong strategy, interpreting a result wrongly, all of which can hinder us from performing effective testing.  On the other hand, visionaries that can unravel the unknown, unknowns in test can reap significant benefits and can positively impact the test community.  The panelists will uncover examples of unknown, unknowns in their areas of test, and the impact (both negative and positive) in their areas of test.   

Panelists:

Y.  Zorian, Synopsis;

K. Chakrabarty, Duke University;

S. Venkataraman, Intel;

D. Armstrong, Advantest;

P. Nigh, Global Foundries;

R. Arnold, Infineon

Title:  The Business of Test:  Test and Semiconductor Economics

Abstract:  Test methodology changes have historically been driven largely by necessity-----critical needs for cost reduction or quality improvements. This history makes possible the prediction of future changes.  Dr. Rhines will review the driving forces for prior discontinuities in Design-for-Test, analyze the rates of adoption of new test methodologies, and discuss the likely forces that will change our test priorities in the future.

WALDEN C. RHINES is Chairman and Chief Executive Officer of Mentor Graphics, a leader in worldwide electronic design automation with revenue of $1.2 billion in 2015. During his tenure at Mentor Graphics, revenue has nearly quadrupled and Mentor has grown the industry’s number one market share solutions in four of the ten largest product segments of the EDA industry. He joined Mentor in 1993 from Texas Instruments (TI) where he was most recently Executive Vice President in charge of TI’s semiconductor business.  Rhines has served five terms as Chairman of the Electronic Design Automation Consortium. He is also a board member of the Semiconductor Research Corporation and First Growth Children and Family Charities.  He received a BSE degree from the University of Michigan, an MS and PhD from Stanford University, an MBA from Southern Methodist University and Honorary Doctor of Technology degrees from Nottingham Trent University and the University of Florida.

Organizer:   Mustapha Slamani: Globalfoundries

Moderator:  Mark Roos, Roos Instruments

Panelists:

Brian Floyd, North Carolina State University

Roger McAleenan, Advantest

Pete Cain, Keysight

Andreas Roessler, Rohde&Schwarz USA

Mustapha Slamani, Globalfoundries

Chris White, National Instruments

The need for 1000x increase in mobile data rate led to a push for an evolution of wireless networks and a revolution in architecture to meet future demands. The current architecture needs some major changes to keep up with future data needs such as:

• Higher analog bandwidth by moving to higher carrier frequencies 28GHz up to 42GHz or more that requires advanced silicon technology nodes
• Beam forming: Higher number of phased array antenna elements to improve signal quality
• Spatial distribution of backhaul networks to increase capacity
• Advance modulation schemes with carrier aggregation and multicarrier waveforms

The corresponding test methods and processes need to evolve to match the new 5G requirements in order to provide a high confidence to operators that the technology and services are implemented according to specification. New challenges are experienced in manufacturing setup such as cooling mechanism and test hardware proximity to the handler and prober environment.  Testing modules with integrated antenna in a production environment requires a complete new thinking, where only wireless communication between the tester and the DUT is possible. This panel will highlight the 5G test challenges and explore possible future solutions to enable mass market production.

Organizer: Haruo Kobayashi, Gunma University, Japan

LSI testing is not just technology, but also it is a part of company management strategies. For example, some companies may use low cost ATE while others may use high-end mixed-signal ATEs as well as its associated services & know how. It also depends on applications of the DUT; for automotive application ICs, reliability and safety are very important and sufficient testing is required. The figure of merit for LSI testing may be Test quality / Test cost. However, even in automotive application cases, test cost reduction is very important as well as test quality. The concept of cost makes LSI testing technology clear.  In this panel, several possible LSI testing methods in terms of test cost reduction will be discussed. The panelist may take a position of e.g., automotive or consumer applications of ICs, testing flow & technology (BIST or BOST, w/ adaptive test or w/o), usage of state of art EDA tools and ATE or usage of conventional tools and equipment, large or small volume of ICs.

Panelists:

Peter Sarson, AMS

Wim Dobbelaere, ON Semiconductor

Robert van Rijsinge, NXP Semiconductors

Bob Barlett, Advantest

Rob Knoth, Cadence

Abstract: IEEE P1838 has come a long way to bridging the gap between other test standards and their application in a 3D-IC test environment. Get updated on their progress at this session.

Session Organizer: Adam Cron, Synopsys

Session presenters:

1. P1838 Overview: Erik Jan Marinissen, IMEC
2. Serial Control Mechanism: Al Crouch
3. Die Wrapper Register: Teresa McLaurin, ARM
4. Flexible Parallel Port: Adam Cron, Synopsys
5. Description Languages: Sandeep Bhatia, Google

*15-minute tributes are devoted to honor Professor Edward J. McCluskey at the end of this keynote session.

TITLE: Hardware Inference Accelerators for Machine Learning

NAME: Rob A. Rutenbar, Professor, UIUC

ABSTARCT:

Machine learning (ML) technologies have revolutionized the ways in which we interact with large-scale, imperfect, real-world  data.  As a result, there is rising interest in opportunities to implement ML efficiently in custom hardware. We have designed hardware for one broad class of ML techniques: Inference on Probabilistic Graphical Models (PGMs).  In these graphs, labels on nodes encode what we know and “how much” we believe it;  edges encode belief relationships among labels;  statistical inference answers questions such as “if we observe some of the labels in the graph, what are most likely labels on the remainder?”  These problems are interesting because they can be very large (e.g., every pixel in an image is one graph node) and because we need answers very fast (e.g., at video frame rates).  Inference done as iterative Belief Propagation (BP) can be efficiently implemented in hardware, and we demonstrate several examples from current FPGA prototypes. We have the first configurable, scalable parallel architecture capable of running a range of standard vision benchmarks, with speedups up to 40X over conventional software.   We also show that BP hardware can be made remarkably tolerant to the low-level statistical upsets expected in end-of-Moore’s-Law nanoscale silicon and post-silicon circuit fabrics, and summarize some effective resilience mechanisms in our prototypes. 

BIO: Rob A. Rutenbar received the Ph.D. degree from the University of Michigan, Ann Arbor, in 1984. From 1984 to 2009, he was faculty at Carnegie Mellon, where he held the Stephen J. Jatras (E’47) Chair in Electrical and Computer Engineering.  In 2010 he joined the University of Illinois at Urbana-Champaign, where he is currently the Abel Bliss Professor and Head of Computer Science.  His research has focused in three broad areas:  tools for a variety of IC design problems;  methods to manage the messy statistics of nanoscale chip designs;  and custom silicon architectures for challenging tasks such as speech recognition and machine learning.   His work has been featured in venues ranging from EETimes to the Economist magazine.   He is a Fellow of the ACM and IEEE. 

Organizer: Yervant Zorian, Synopsys

Moderator: Hans-Joachim Wunderlich, University of Stuttgart (wu@informatik.uni-stuttgart.de)

Four Speakers:

Davide Appello, ST (davide.appello@st.com)

Christophe Eychenne, Bosch (CHRISTOPHE.EYCHENNE@fr.bosch.com)

Riccardo Mariani, Intel (riccardo.mariani@intel.com)

Yervant Zorian, Synopsys (Zorian@synopsys.com)

Automakers worldwide are on an aggressive path to change the way we use our cars - whether driven by ourselves, or left to an autonomous "smart" system get us to our destination. Their emerging strategy is to design smart, reliable, secure, and safe connected cars. These trends present additional challenges for automotive IC designers to meet higher quality and reliability goals, along with legacy demands for in-vehicle cost effectiveness and time-to-market. This special session will address today's challenges and solutions to address the above through presentations by ecosystem representatives.

Title: Addressing Semiconductor Industry Needs: Defining the Future through Creative, Exciting Research

Ken Hansen, CEO
Semiconductor Research Corporation

Abstract:
In the history of the semiconductor industry, there has been no other period in time with as much uncertainty in the way forward. But with uncertainty comes great opportunity. There is a need for transformative innovation fueled by breakthrough research to reinvigorate the growth of the industry. This talk will identify some of the new exciting challenges the industry is facing and research areas where investment is needed address them. Systems of the future – autonomous vehicles, internet of things, self-adaptive configurations modeled on biology – will require advanced techniques to test them, secure them, reduce their power, and produce them without error. This increase in complexity coupled with a decreasing ability to rely on deterministic circuits requires new approaches to be created by cross-disciplinary teams co-optimizing across the entire design hierarchy space.

Bio: Ken Hansen joined Semiconductor Research Corporation as its President and CEO in June 2015. Ken brings his experience as the former Vice President and Chief Technology Officer with Freescale Semiconductor. Prior to becoming CTO at Freescale, Ken was Vice President and led Freescale’s Chief Development Office where he improved design efficiency and reduced product cost for all Freescale business units. Previously, he held several senior technology and management positions at Freescale and Motorola leading research and development teams. He received the BSEE and MSEE degrees from the University of Illinois where he also has been recognized as an ECE and College of Engineering Distinguished Alumni, is a Fellow of the IEEE, and holds 11 U.S. patents. Ken is an industry veteran, with 40 years of experience in technical management and system/circuit design, primarily in the area of wireless communications.

Organizer: Bruce Parnas, Applied Materials

Every few years industry trends drive changes in the requirements for test equipment. This panel will look at trends in the last five years and the impact on ATE as well as look into the future.

Panelists:

Paul Berndt, Cypress Semiconductor

Holger Engelhard, Advantest

Qi Fan, Huawei

Ken Lanier,Teradyne

John Shelley, XCerra

Organizer: Mark M. Tehranipoor, University of Florida

Abstract: IoTs are expected to be pervasive in home, businesses, smart communities and cities. IoT devices are now found in commonplace amenities such as cars, phones, watches, appliances, home and business security systems, thermostats, smoke detectors, as well as applications such as utilities, banking, transportation, energy, and (bio)medical industry. The number of devices introduced in the market as IoT has increased drastically, with an estimated 50 billion by 2020, most of which are expected to be fabricated off-shore.

The massive deployment of IoT devices and the shortened time-to-market has led to significant challenges including (i) testing, (ii) validation, and (iii) security and privacy concerns. This has left devices with many unintentional bugs and security vulnerabilities, which can cause data leakage, denial of service, and malicious modification of devices physically and/or remotely. The panelists will discuss the challenges that comes with such large scale growth of IoT devices in terms of test and validation. Further, end-to-end authentication from device-to-system, especially throughout the modern complex supply chain is also discussed.

Panelists:

Yousef Iskandar, Cisco, Confirmed

Michael Schuldenfrei, Optimal +, Confirmed

Michal Vai, MIT Lincoln Lab, Confirmed

Yervant Zorian, Synopsys, Confirmed