ABSTRACT. Diagnostic resolution is improved, without degrading accuracy, of a population of defects thru the application of machine learning. Resolution is improved even further through careful selection of failed chips for physical failure analysis.

ABSTRACT. An industrial-scale diagnostic ATPG tool is presented. Silicon results collected on Intel^® microprocessor at wafer sort demonstrated 2.8X to 3X improvement in diagnostic resolution with the proposed content compared to an industry standard DATPG content.

ABSTRACT. This paper introduces a technique to handle wrong failure mappings in diagnosis with modern day extreme low pin compressors. The proposed feature can achieve scan level diagnosis accuracy even with compressed responses.

ABSTRACT. The problem of performing diagnosis using production test results in a test compression environment is addressed. The key idea is to use symbolic canceling in MISR signatures to improve existing diagnosis procedures.

ABSTRACT. The paper presents a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points.

ABSTRACT. We present a unified test technique that targets all the components of a network-on-chip design by using a new fault-tolerant multicast procedure. Test packet delivery avoids all faulty components to prevent corrupting test data.

ABSTRACT. Cell-aware faults require more patterns and are harder to detect than stuck-at faults. We show that capturing data at flip-flops during scan shift can enhance cell-aware fault detection while maintaining stuck-at pattern counts.

ABSTRACT. The paper presents a method to minimize silicon area needed to implement conflict-aware test points. By reusing the significant majority of functional flip-flops as control point drivers the method achieves remarkable pattern count reductions.

ABSTRACT. SOCs implementing high bandwidth systems frequently use multi-port memories.. The most area efficient implementation uses a single port SRAM core running at double the frequency of the periphery, enabling 2 external ports to operate into a single port core. This is known as a double-pumped two-port or dual-port memory. These memories improve system performance; however there is a lack of accurate fault models to be used for fault coverage analysis. This paper establishes double pumped memory faults (DPMFs), based on the concept of fault primitives [4]. New March based test algorithms are proposed to detect each class of proposed fault model. The algorithms are designed to reduce area overhead by exploiting the March test symmetry. The algorithms are implemented using a commercially available BIST controller. Experimental results prove the BIST test can detect faults in single/double pumped performance by using shmoo data.

ABSTRACT. As the complexity of Integrated Circuit Testers increases, delivering and maintaining consistent performance to the full range of specifications becomes much more challenging. Supplier diagnostic and calibration procedures are not full coverage nor are written in the end user application environment. The TPV process is a software/hardware combination consisting of a test program written in the user application environment and a loopback DIB with specific routing that allows for tester instruments to test themselves and validate their electrical spec adherence. Each of the millions of test points logs parametric data which in turn enables the analyses of tester performance against the supplier's published electrical specs, thereby highlighting diagnostic escapes, calibration coverage issues and instrument quality problems. Specific examples of tester noncompliance and supplier feedback are shown.

ABSTRACT. Locking segment insertion bits (LSIBs) can be used to help secure on-chip embedded instruments. They are difficult to break through brute force, but they may be vulnerable to side channel attacks. This poster explores different LSIB key-logic implementation approaches to mitigate power analysis attacks on LSIB keys.

ABSTRACT. Modern SoC FPGA systems contain increasing number of embedded hard IPs, designed in typical ASIC methodology and reside outside configurable logic. High reliability levels can be achieved by continuously testing the fabric and embedded IPs throughout system lifetime. Fabric can be engineered to serve as an in-situ ATE to test the different IPs.

ABSTRACT. This poster will explore the state of the art for boundary-scan-based testing (BST) of double-data-rate (DDR)-class memory. As mission operation of memory grows more complex with each generation, the facility to implement conventional BST memory access verification diminishes as does the effectiveness of the resultant test coverage. The most recent DDR generations, DDR4 SDRAM and GDDR5 SGRAM, have introduced special connectivity test modes, which promise great returns for test generation facility and test coverage effectiveness. But, these come with some design-for-test (DFT) burdens, not only for boards and systems, but for chips as well, that need due consideration for success. Accordingly, the poster will present the test generation and test coverage challenges of extant methods, extend DFT guidance for the new methods, and demonstrate success for boundary-scan-based methods.

ABSTRACT. Dynamic Bandwidth Management (DBM) for testing SoC designs plays a key role in reducing test cost. Another popular hierarchical test approach is based on Channel Sharing (CS) plus Pattern Retargeting (PR). In this poster, we compare DBM vs. (CS + PR) by using one of our designs as an example. The test results illustrate that using DBM we can save ~40% more patterns comparing to (CS + PR).

ABSTRACT. Photonic NoC (PNoC) is emerging as a promising alternative to address the power-performance trade-off in traditional electrical NoC. Ultra speed photonic routers and silicon waveguides are used to realize fast switching and low-power communication in a PNoC. A photonic router consists of microring resonator (MRR) based switches and photonic waveguides. However, photonic components are highly susceptible to process and thermal variations leading to runtime faults. These faults can occur in MRRs, waveguides, routers, and IPs. This work proposes a fault-tolerant photonic router design for low-power, and high-performance PNoC with high reliability. The PNoC hosts a concurrent built-in-self-test (BIST) unit which tracks MRR health and provides early notice if an MRR is faulty. The proposed photonic router has 4 redundant MRRs. Whenever there is an MRR fault, the BIST unit signals the router controller and the router controller activates the neighboring redundant MRR and then the transmission is re-initiated. A retransmission buffer has been incorporated to facilitate packet re-transmission in case of runtime packet loss. The placement of MRRs ensures use of minimal space (hardware) and time (retransmission) redundancy for lossless packet transmission. We also propose a fault-tolerant control module. This module uses a fault-tolerant routing algorithm ensuring deadlock and livelock free transmission. We have analyzed the cost of incorporating fault tolerant design features in a PNoC. The four frontiers targeted here are concurrent BIST, hardware redundancy, time redundancy, deadlock and livelock resolutions units for lossless transmission. Our analysis shows significant improvements in reliability while maintaining expected throughput compared to recently reported results. We simulated the proposed design using a system level simulator running the PARSEC benchmark suite. We demonstrated 98.4% network throughput with 3% faults, and 89.2% network throughput with 20% faults. These results come with a 35% reduction in the number of MRRs compared to a conventional crossbar-router and 40% reduction compared to a lambda-router. Simulations of the electrical control module and router show that the proposed PNoC with an area of 20,000 µm2 consumes 3.8 mW/router at 600 MHz.

ABSTRACT. In FinFET technology the fabrication process has many different steps compared to the traditional planner technology that may introduce a new set of defects. In order to effectively diagnose these new defects, the UDFM file needs to be enhanced to model them accurately first. In addition, cell aware diagnosis needs to be able to utilize such information during diagnosis. Furthermore, the volume diagnosis based yield learning flow can be enhanced by making better use of the improved CAD results. In this work we propose a flow to effectively diagnose cell internal defects for FinFET technologies, and validate it on real silicon cases from a 10nm FinFET process.

ABSTRACT. In this paper, a Faster-than-at-Speed-Test technique is approached with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of functional test programs, partly regardless of system behavior preservation. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults.

ABSTRACT. Layout awareness can improve the accuracy of fault models and/or fault coverage . Previously, as an application of layout-aware fault coverage estimation, we proposed test pattern reordering based on target fault selection considering the critical area of every fault. In this study, we propose a two-step test pattern generation that considers weighted bridges and open fault coverage in order to develop fast and compact test pattern set generation. Test pattern reordering is only applied to the second pattern set, which is generated for the residual faults of the first small pattern set.

ABSTRACT. On ATE debug has traditionally involved “2 on a Piano Bench” — one person that understands how to operate the ATE and another person that understands the test and debug features and operations of the chip. More and more of the test and debug features of modern Microprocessors, SoCs, ASICs, ASSPs and even FPGAs are accessed through the JTAG port, and are organized under JTAG 1149.1 instructions, in 1500 wrappers, or on 1687 embedded instrument networks. When these chips are on development, application, or system boards then JTAG tester hardware and software deal with the debug features in a protocol-aware manner with intuitive user interface software. When these chips are in an ATE, a chip engineer that has a high knowledge of the chip must create vectors that must be converted and applied using the ATE — and results must be captured and evaluated — leading to a large turn-around time between applications. A common way of making this process more efficient is to use a JTAG/IJTAG software tool to operate the chip’s test and debug logic, and coupling this to a chip in an ATE by physical connection on the load-board and ATE features such as breakpoints — but with manual operation of each so that the ATE drives functional signals while a different JTAG/IJTAG HW/SW system drives the JTAG port. Typically, the ATE would drive a pattern to achieve a particular state and would be operated to a breakpoint, then the JTAG/IJtAG software would apply a JTAG pattern that enables data capture, debug instrument setup, or data/settings modification. The ATE would then continue to observe the results. Coordination of these steps is time consuming and error prone.

Advantest and SiliconAid have begun investigating an even more unified environment of using JTAG/IJTAG embedded instrument software that uses IJTAG PDL and ICL coupled directly to the ATE sequencer so that it drives the JTAG port through ATE channels. This will allow JTAG or IJTAG sequences to be embedded into a pattern with the ATE controlling features such as clock-control, additional functional pins, breakpoints, triggers, and pin comparators. This enables debug to be accomplished by only one person who can operate an ATE and can use embedded instrument maps to operate chip debug and test features. The resulting test sequence can be driven and viewed directly on the ATE with the debug process accomplished immediately after data is taken and evaluated. The IJTAG embedded IP being used can be highlighted with a chip embedded IP map. The user could modify and edit PDL for a specific IJTAG instrument and software would regenerate the pattern and load into ATE memory. Enhanced debug features could be available to illustrate the data being observed at the embedded IP level. This poster will highlight the EDA IJTAG network software, the ATE features needed, the proposed method of use, and the advantages of this close coupling.

ABSTRACT. ISO 26262 mandates automotive systems to perform real-time monitoring of their function in order to detect sudden hardware defects. A key figure used in this standard is the Diagnostic Coverage (DC) – the percentage of critical hardware defects that are detected by a system’s safety mechanism in real time. The DC can be assessed by injecting faults and simulating -if the ICs functional output is modified due to the fault, and - if the safety mechanism detects the fault. Unlike stuck-at faults typically used for such fault injection, ISO 26262 recommends transient faults to be injected. Transient fault simulation consumes enormous simulation capacity and hence led to prohibitively long simulation times. Only recently, commercial EDA tools that drastically reduce run time become available. DC values calculated for a mid-size IC using commercial EDA tools are presented, compared and discussed.

ABSTRACT. Given the importance of core router in the core network, any failure/fault occurrences can have fatal and wide impacts. With the ever increasing complexity of network products, the failure rate of hardware is rising dramatically. Hence, how to ensure the reliability of network products has become a big challenge. A hardware self-healing technique based on hardware design strategy is proposed in this poster. By applying four types of key technologies, the failure rate of hardware can be effectively reduced. Failing hardware can be self-healed while software not aware. As such, hardware can continue running uninterrupted. Network products usually contain key hardware components/modules such as ASIC/CPU, clocks, power supplies, RAM and buses. In practice, product issues are usually due to failures/faults with RAM, power supplies, clocks and buses. The quality of ASIC itself is not discussed in this poser. For RAM, failure mode contains single-bit failure and multi-bit failure. Single-bit failure can be solved using ECC in current design, while multi-bit failure is a major challenge. Analysis shows that multi-bit failure usually centers around one raw or one bank. Hence, back-up storage resources can be reserved at early design stage. The reserved RAM resources can replace the fault RAM online while system detects multi-bit failing, so that system runs uninterruptedly. Crystal and oscillators are with the highest failing rate among clock system. Clock synthesizer can be used to reduce the amount of individual crystal and oscillators to guarantee system reliability. Further, for key clock sources, double crystal back-up technique can be used to largely improve clock system reliability. Specifically, key crystal is monitored continuously and is replaced by back-up crystal once malfunctioning is detected. System buses such as SerDes support redundancy and back-up mechanism in nature. Difficulties in design thus lie on the control bus channels. We propose to use Escape_BUS to enhance reliability of control bus. Specifically, other bus channels can be used as back-ups for the original bus channel. Key control bus is monitored real-time and can be replaced by the back-up bus immediately one malfunctioning is detected. As such, CPU is still able to communicate to ASIC using the Escape_BUS in case of key control bus failing. Power is probably the module that fails most on board. Its high failing rate and severe failing mode can cause ASIC malfunction and/or damage, especially for high power supply. Multi-phase VRMs are commonly used for large current power supply. An innovative Resource_Pool power supply technique is proposed by Huawei. Top MosFet over current protection mechanism is applied first to prevent ASIC burning. Then, monitoring circuitry is used to monitor working condition of each phase. Detected malfunctioning phase is removed automatically so that power supply functions without any interruption. To sum up, four techniques are proposed such as RAM back-up resource replacement, Resource_Pool power supply, Redundant clock solution and Escape_BUS to effectively solve hardware reliability (except for ASIC) issues, achieving hardware system uninterrupted functioning regardless failing conditions.

ABSTRACT. An 11-value algebra is used to improve path delay fault coverage in KLPG testing of circuits with non-scan flip-flops. Results on ISCAS89 circuits show that with 10% non-scan flip-flops, path coverage increases by an average of 90% for robust test, transition fault coverage increases by an average of 70%, and CPU time per path falls by 40%.

ABSTRACT. Attached as PDF

ABSTRACT. Tests are very sensitive to the power supplies. In multi-site testing, if the impedances of Power Delivery Network (PDN) on different sites are different due to layout trace or different capacitance values, it may cause serious yield loss due to IR drop on different PDNs. In this poster, we propose a solution such that test engineers and DIB designers can optimize the DIB impedances at the sensitive frequency points to minimize the yield loss due to IR drop on PDNs during testing.

ABSTRACT. IEEE 1687-2014 is a new standard that brings management, optimization and scalability of growth to the access and operation of embedded instruments contained within semiconductor devices. The current standard teaches IEEE 1149.1 as the natural device pin-interface and controller to access and operate the 1687 network, although the standard allows for other device pin-interfaces and controllers through a generic Instrument Connectivity Language (ICL) construct known as an AccessLink. A great many chips in the electronics industry do not support the 1149.1 TAP, and use alternate interfaces to access test, debug, monitor, and configuration resources and instruments. 1687 could be beneficial at the board level and at the IC test and debug level if used in these chips that have these alternate interfaces and controllers such as I2C, SPI, USB, AMBA and other device pin-interfaces. An effort to formalize this access was started as a study group at ITC 2015 and in May 2016 a PAR was submitted to start a Standard's Working Group - "Standard for the Application of Interfaces and Controllers to Access 1687 IJTAG Networks Embedded within Semiconductor Devices". The work done so far, which will be presented in this poster, includes defining the work product to create the new standard and a hardware architecture that changes the 1687 retargeting process from a Shift-Capture-Update-Reset assertion signal interface, to an iScan Packet interface that uses command (CMD) and serial data (DATA) elements. This allows any given interface to operate a 1687 network by only sending data transactions to a "decoupling FIFO interface".

ABSTRACT. Today's very large SoC designs present significant DFT Challenges. The large number of blocks relative to the number of limited chip pins makes it difficult to efficiently allocate scan channels for the fewest patterns. The large design size also requires significant machine memory and ATPG runtime to generate patterns. This industry case study shows how hierarchical DFT techniques were used to address the design size challenges and scan channel sharing provided the embedded compression logic with additional channel capacity. Data is shared on the results achieved.

ABSTRACT. Introduction The advantage of Part Average Testing (PAT) during production has been demanded not only for automotive products but the RF devices as well. Also the case that under final test condition the IC identified as outlier needs to be sorted out immediately but no way as post-process like wafer sort. In this paper the solution which implements Real-Time Dynamic Part Average Testing (DPAT) in ATE OS with no impact on production sequencer control and testing throughput is introduced. By applying this methodology the benefit of using the smart way to perform DPAT without extra codes and plug-in libraries in test program will be demonstrated.

Method SG9000, which is the ATE designed by Sigurd Microelectronics Corp., builds with the own software environment SGOS to conduct overall process control including production sequencing as well as test program execution and datalog generation. By its embedded core engine with real-time processing in tested results before generating datalog, also following the rules defined in AEC Council AEC-Q001 Rev-D, the DPAT in SGOS with Real-Time feature is implemented, see Fig. 1, so that it can identify the desired test items and complete DPAT under the requested number of samples, meanwhile apply the binning with outliers rejected and recorded in datalog without commercial production monitoring software needed. Furthermore, not only single-site testing but also multi-site running equip with such real-time function, with no any changes in test program but provide the alternative in SGOS to activate DPAT.

Extending the feature we can monitor IC stack-up, which is the malfunction during handler operation, by software analysis rather than relying on handler sensor in case of hardware error potentially. Through statistic calculation with pre-defined number of samples and target standard deviation, any occurrence of IC stack-up can be distinguished by SGOS software, explained in Fig. 2.

Results Actual data collected from production will be presented as the outlier identified and rejected during operation. In conclusion SGOS Real-Time DPAT in SG9000 helps customers with testing quality assured with no extra commercial software required for data processing.

ABSTRACT. E-beam probing with Scanning Electron Microscope (SEM), Laser voltage imaging (LVI) and Laser Voltage Probing (LVP) are valuable tools that are being used in advanced debug for logic, memory and FPGA devices over the past several years. E-beam, LVI, and LVP equipment generally require the IC to be electrically stimulated through an ATE tester. In this poster we describe an innovative service oriented test solution which is used by Xilinx with diagnostic equipment for debugging high end FPGA devices. The Cloud Testing Service reduces overall test development, debug and new silicon validation costs while providing the same capabilities of a traditional ATE tester.

ABSTRACT. It has been shown, that the degradation of the clock frequency in processor cores during lifetime can be monitored by measuring IDDT values. This can be carried out in a pseudo on-line testing manner. It also requires functional testpatterns with regard to the proper processor workload. We present an IDDT monitor which is compatible with the standard IEEE 1687. By using this standard, one can configure the monitor in the proper modes (e.g. set the window) and subsequently measuring the currents. The measurements can be carried out via a TAP during final test, or internally during lifetime via an IJTAG controller. It opens the road for zero mean downtime, and a significantly increased reliability in the case of homogeneous multi-processor SoCs.

ABSTRACT. High performance reliable designs on Deep sub micron technology utilize multiple reused instances of unique functional logic blocks / cores in construction of System-On-Chips. Such design may offer multiple functional aspects based on the number of reused instances which pass manufacturing test. This requirement demands the test to isolate the criteria that qualifies one or more functionality with which the wafer may be packaged, based on test results. Thus it is inevitable to plan on test generation and scheduling such that the pass/fail status of the reused cores or logic blocks can be observed on the fly during manufacturing test with pattern reuse and pattern volume reduction. This Poster illustrates a Novel approach that arrange the reused instances of multiple IEEE 1500 wrapper bound Logic Blocks or Cores in the rows and columns of a matrix, based on following rules. 1. Every column has the same module. 2. Parent row or the bottom row must contain all unique type of modules. 3. Test is scheduled on one row at a given instance of time. 4. Each reused cores incorporates Compression with serial signature observation. 5. Modules in the parent row are directly observed on the scan out pins. 6. Modules appearing in non-parent row propagates the signature in a multiplexed daisy chain manner that passes through the parent row. The Test Architecture also facilitates 1. On the fly isolation of the module/s that fail the manufacturing test. 2. Turnaround time improvement in pattern generation and test time. 3. Efficient pattern generation, pattern reuse and pattern volume reduction compared to conventional methods of reused core tests. 4. Better pattern compaction approach based on functional requirements to qualify the manufactured chip. A table summarizing the existing result would also printed to show the efficiency of this architecture with reference to the claims aforementioned.

ABSTRACT. A scalable and reusable framework for lifetime dependability management of complex Systems-on-Chips (SoCs) is presented in this work based on the IEEE 1687 standard. IEEE 1687 Procedural Description Language (PDL) is used to implement dependability procedures that use embedded instruments. An on-chip Dependability Manager (DM) executes the compiled dependability procedures during the SoCs lifetime. Dynamic patterns retargeting of instruments patterns is implemented on-chip for enabling the execution of procedures with control-flows dependent on the run-time data. IEEE 1687-based interrupts localization and servicing is also supported using this framework. By adhering to the IEEE 1687 standard, this framework could be reused for any iJTAG-enabled SoC for dependability management.

ABSTRACT. 35-word abstract: Devices that are designed to operate in a low power environment require special consideration during test. The capability to reduce switching activity during test must be enabled through test logic and pattern sets that can be adjusted post-silicon.

Complete Abstract:

Devices that are designed to operate in a low power environment require special consideration during test. Some of these designs use functional clock gates on nearly 100% of the sequential logic which can allow switching activity on as low as 5% of the logic during functional mode. Though shift frequency is much slower than functional frequency, the instantaneous IR drop for close to 50% of the sequential elements switching may be too much for the power infrastructure designed for functional mode. Consideration must also be made for at-speed capture cycles as they will generally have a much higher switching activity than functional mode. There must be careful consideration for at-speed delay tests, especially if they will be used for speed binning or screening. In addition memory BIST algorithms can stress the power infrastructure of memories much more than functional mode usage while the logic surrounding the memories may be stressed less. Power simulation tools have not been very accurate when determining whether or not scan or MBIST patterns will function properly. The capability to reduce switching activity during test must be enabled through test logic and pattern sets that can be adjusted post-silicon.

ABSTRACT. Test power consumption has become one of main concerns when applying scan-based tests. DFT techniques used to reduce both shift and capture power for industrial designs are discussed to minimize thermal issues and power supply noise during test application.

ABSTRACT. Power demand inside mobile devices has dramatically increased. Aggregate current ratings of typical PMICs are pointing to well beyond 50 A. But how can you test that, at consumer cost level, with standard ATE?

ABSTRACT. Integrated DC-DC converters using HVCMOS can experience significant ringing at the output switching node due to the parasitic in standard IC packages. This talk will focus on the SOA of the output stage in a buck configuration.

ABSTRACT. We illustrate that memory repair for high fault rates allows improving yield, extending circuit life, reducing power, and improving reliability. Then we present several new concepts enabling low-cost memory repair for high fault rates.

ABSTRACT. Output-bit selection methodology and implementations for test response compaction are presented, which have advantages of zero aliasing, high compaction ratio (generally greater than 90%), full X-tolerance, low area overhead, simple test control and high diagnosability.

ABSTRACT. Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. This work provides solutions to new challenges related to testing of 2.5D ICs. We propose a test architecture using e-fuses for pre-bond interposer testing. We design a test architecture that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. We present an efficient built-in self-test (BIST) technique that targets the dies and the interposer interconnects. We next describe two efficient ExTest scheduling strategies that implement interconnect testing between tiles within a system on chip (SoC) die on the interposer. Finally, we present a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

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ABSTRACT. Covering the diagnosis part and discuss techniques to improve diagnosis resolution and precision.

ABSTRACT. Covering the failure isolation from physical fault isolation tools: Optical and Electrical probing tools and failure analysis step including SEM and TEM.