Program for Tuesday, November 15th: Talk View

PROGRAM FOR TUESDAY, NOVEMBER 15TH: TALK VIEW

Days:

previous day

next day

all days

View: with abstracts session overview

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

19:00

19:30

20:00

20:30

09:00-09:30 Plenary - Opening Session

09:30-10:30 Keynote: Walden C. Rhines, CEO of Mentor Graphics

14:00-14:30

Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis

Yang Xue, Xin Li, Ronald Blanton, Carlston Lim, M. Enamul Amyeen

14:30-15:00

A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation

Amyeen, Kim, Chandrasekar, Noman, Venkataraman, Jain, Goel, Sharma

15:00-15:30

Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution

Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur

15:30-16:00

Using Symbolic Canceling to Improve Diagnosis from Compacted Response

Kamran Saleem, Nur Touba

14:00-14:30

Test Point Insertion in Hybrid Test Compression / LBIST Architectures

Jerzy Tyszer, Nilanjan Mukherjee, Janusz Rajski, Elham Moghaddam, Justyna Zawada

14:30-15:00

A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs

Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara

15:00-15:30

Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift

Zhang, Hwong, Sun, Garcia, Alhelaly, Shofner, Winemberg, Dworak

15:30-16:00

Minimal Area Test Points for Deterministic Patterns

J. Tyszer, Y. Liu, E. Moghaddam, N. Mukherjee, J. Rajski, S. Reddy

14:00-14:04

Double Pumped Memory Fault Modeling and Test

Saman Adham, Jiunn-Der Yu, Amy Lai, Cormac O'Connell, H.J. Liao

14:04-14:08

Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance

Nelson Magdaleno, Mobashir Mohammed

14:08-14:12

Does your Locking SIB have a Back Door?

S. Kancharla, S. Gupta, J. Kayse, J. Dworak, A. Crouch, D. Engels

14:12-14:16

Custom Logic BIST in cutting edge SoC FPGA systems

Raghuraman Rajanarayanan, Namit Varma, Adam Cron

14:16-14:20

Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based

Adam W Ley

14:20-14:24

Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns

Kenneth Huang, Tim Li, Liuming Xu, Binghua Lu, Yu Huang, Fanjin Meng

14:24-14:28

Fault Tolerant Photonic Router for Network-on-Chip with High Reliability

Dharanidhar Dang, Prasenjit Biswas, Duncan Walker, Rabi Mahapatra

14:28-14:32

Diagnosing Cell Internal Defects for FinFET Technology

Huaxing Tang, Dong Kwan Han, Wu Yang, Mohammed Abdelwahid, Stephen Park

14:32-14:36

Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test

A. Bosio, P. Bernardi, G. Di Natale, A. Guerriero, F. Venini

14:36-14:40

Note on Critical-Area-aware Test Pattern Generation and Reordering

Shingo Inuyama, Kazuhiko Iwasaki, Masayuki Arai

14:40-14:44

Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools

Alfred Crouch, Jim Johnson, Neils Poulson

14:44-14:48

Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262

Jan Schat

14:48-14:52

Uninterrupted Hardware Design

Xiaopeng Qin, Hua Li, Zhiyuan Wang

14:52-14:56

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

Duncan Walker, Prasenjit Biswas

14:56-15:00

ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement

Douglas Sprague, Ray Bulaga

15:00-15:04

Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board

Jintao Shi, Zaiman Chen, Yu Huang, Peilai Zhang

15:04-15:08

1687.1 -- New Connections for a New Standard

Alfred Crouch, Jim Johnson, Martin Keim

15:08-15:12

Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC

Zhigao Zhang, Luning Kong, Kenneth Huang, Binghua Lu, Rick Fisette, Fanjin Meng

15:12-15:16

A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production

Cheng-Hung Tsao, Yu-Tang Hsu

15:16-15:20

CloudTesting Service In Silicon Diagnostics

At Sivaram, Oyama Yasuji, Benhai Zhang, Dave Mark, Jenny Fan

15:20-15:24

An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics

Hans Kerkhoff, Ahmed Ibrahim

15:24-15:28

Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous

B. Konda, J. Udyavar, S. Ahmed, S. Kumar, M. Lakshmanan

15:28-15:32

Scalable and Reusable Dependability Framework Based on IEEE 1687

Ahmed Ibrahim, Hans Kerkhoff

14:00-14:30

DFT Test Considerations for Low Power Devices

Teresa Mclaurin

14:30-15:00

Scan-Based Low Power Test Generation

Xijiang Lin

15:00-15:30

Got the Power? Test and DfT of Mobile Power Management ICs (PMICs)

Hans Martin von Staudt

15:30-16:00

Transient Testing of Integrated Power Output Stages

Wai Tung Ng

14:00-14:30

Memory Repair for High Fault Rates

Panagiota Papavramidou

14:30-15:00

Output Bit Selection Methodology for Test Response Compaction

Wei-Cheng Lien, Kuen-Jong Lee

15:00-15:30

Testing of Interposer-Based 2.5D Integrated Circuits

Ran Wang

16:30-18:00 Panel: Phased Array 5G: Is Test Connected or Disconnected?

16:30-18:00 Panel: Test Cost Reduction--Is There More to Cut?

16:30-18:00 3D-IC Test Standard IEEE P1838

16:30-17:00

The Enemies of IC Security and Trust and How to Test Them

Bhunia Swarup

17:00-17:30

Is Automated Testing the Panacea Cryptography Needs to Deliver Promised Security Assurances?

Apostol Vassilev

17:30-18:00

Hardware Security Assurance: Challenges and Opportunities

Amir Khatibzadeh

16:30-17:15

The Journey to root cause - Part I

Enamul Amyeen

17:15-18:00

The Journey to root cause - Part II

Andres Maldonado

18:45-20:45 ITC Welcome Reception