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09:00-10:30 Session 14: ATE II
Gordon Roberts (McGill University, Canada)
Masahiro Ishida (ADVANTEST Corporation, Japan)
Toru Nakura (the University of Tokyo, Japan)
Naoki Terao (the University of Tokyo, Japan)
Masahiro Ishida (Advantest Corporation, Japan)
Rimon Ikeno (the University of Tokyo, Japan)
Takashi Kusaka (Advantest Corporation, Japan)
Tetsuya Iizuka (the University of Tokyo, Japan)
Kunihiro Asada (the University of Tokyo, Japan)
Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
SPEAKER: Naoki Terao

ABSTRACT. This paper proposes a technique to adjust the power supply impedance of an ATE to that of a customer board to eliminate overkills and underkills coming from the impedance difference between the two environment.

Masahiro Murakami (Gunma University, Japan)
Haruo Kobayashi (Gunma University, Japan)
Shaiful Nizam Bin Mohyar (Universiti Malaysia Perlis, Malaysia)
Osamu Kobayashi (D-Clue Technologies, Japan)
Takahiro Miki (Gunma University, Japan)
Junya Kojima (Gunma University, Japan)
I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems

ABSTRACT. This paper describes application of a complex band-pass delta-sigma  DA modulator to I-Q signal generation for I-Q balance testing of communication IC as well as ATE system usage, and presents its extention techniques.

Takayuki Nakamura (ADVANTEST CORPORATION, Japan)
Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique

ABSTRACT. This paper describes a fast and low cost crosstalk measurement method. Only a single measurement makes it possible to evaluate the crosstalk from a huge number of transmission lines by inputting clock at various frequencies.

09:00-10:30 Session 15: Reliability
Wim Dobbelaere (ON Semiconductor, Belgium)
Shi-Yu Huang (National Tsing Hua University, Taiwan)
Mehdi Sadi (University of Florida, USA)
Gustavo Contreras (University of Florida, USA)
Dat Tran (NXP Semiconductor, USA)
Jifeng Chen (NXP Semiconductor, USA)
Leroy Winemberg (NXP Semiconductor, USA)
Mark Tehranipoor (University of Florida, USA)
BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
SPEAKER: Mehdi Sadi

ABSTRACT. In this paper, we present a novel methodology, BIST-RM, to accurately predict the degradation due to aging mechanisms in a SoC at run-time by utilizing the existing LBIST hardware and software implemented Machine Learning classifier. 

Suvadeep Banerjee (Georgia Tech, USA)
Abhijit Chatterjee (Georgia Tech, USA)
Jacob A. Abraham (University of Texas at Austin, USA)
Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States

ABSTRACT. Safety and reliability requirements necessitate development of real-time error detection in nonlinear control systems. This work proposes a methodology for detecting sensor degradation, actuator malfunctions and soft errors in program execution of the control algorithms.

Alessandro Vallero (Politecnico di Torino, Italy)
Alessandro Savino (Politecnico di Torino, Italy)
Gianfranco Michele Maria Politano (Politecnico di Torino, Italy)
Stefano Di Carlo (Politecnico di Torino, Italy)
Athanasios Chatzidimitriou (University of Athens, Greece)
Sotiris Tselonis (University of Athens, Greece)
Manolis Kaliorakis (University of Athens, Greece)
Dimitris Gizopoulos (University of Athens, Greece)
Marc Riera Villanueva (UPC, Spain)
Ramon Canal (UPC, Spain)
Antonio Gonzalez (UPC, Spain)
Maha Kooli (LIRMM, France)
Alberto Bosio (LIRMM - Universit de Montpellier II / CNRS, France)
Giorgio Di Natale (LIRMM, France)
Cross-Layer System Reliability Assessment Against Hardware Faults

ABSTRACT. Accurate early estimation of system reliability facilitates the integration of effective protection mechanisms against hardware faults. We propose a scalable, cross-layer methodology and supporting tools for accurate but fast estimations of computing systems reliability. 

09:00-10:30 Session 16: Test Generation
Greg Maston (Synopsys, USA)
Tim Ayres (Synopsys, USA)
Cheng-Hung Wu (National Cheng Kung University, Taiwan)
Kuen-Jong Lee (National Cheng Kung University, Taiwan)
Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement
SPEAKER: Cheng-Hung Wu

ABSTRACT. This paper presents a systematic approach to transform various fault models to a unified model such that all faults can be dealt with simultaneously by using an ATPG tool for aggressor-victim bridging fault model.

Huina Chao (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Huawei Li (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Tiancheng Wang (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Xiaowei Li (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Bo Liu (Beijing Institute of Control Engineering, China)
An accurate algorithm for computing mutation coverage in model checking
SPEAKER: Huina Chao

ABSTRACT. This paper presents an accurate algorithm to compute mutation coverage for properties written by arbitrary CTL formulas. Experimental results show it can identify a great number of covered states missed by previous methods.

Kuen-Jong Lee (National Cheng Kung University, Taiwan)
Pin-Hao Tang (National Cheng Kung University, Taiwan)
Michael Kochte (ITI, University of Stuttgart, Germany)
An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
SPEAKER: Kuen-Jong Lee

ABSTRACT. All test data are stored in a novel scan chain architecture such that the stored data can be extracted, reconstructed and decompressed into full-coverage deterministic patterns using an on-chip test controller and a pattern decompressor.

09:00-10:30 Session S8: Special Session - Automotive IC Quality & Reliability: Today's Challenges & Solutions

Organizer: Yervant Zorian, Synopsys

Moderator: Hans-Joachim Wunderlich, University of Stuttgart (

Four Speakers:

Davide Appello, ST (

Christophe Eychenne, Bosch (

Riccardo Mariani, Intel (

Yervant Zorian, Synopsys (

Automakers worldwide are on an aggressive path to change the way we use our cars - whether driven by ourselves, or left to an autonomous "smart" system get us to our destination. Their emerging strategy is to design smart, reliable, secure, and safe connected cars. These trends present additional challenges for automotive IC designers to meet higher quality and reliability goals, along with legacy demands for in-vehicle cost effectiveness and time-to-market. This special session will address today's challenges and solutions to address the above through presentations by ecosystem representatives.


Hans-Joachim Wunderlich (University of Stuttgart, Germany)
11:00-12:00 Session K2: Keynote: Ken Henson, CEO of SRC

Title: Addressing Semiconductor Industry Needs: Defining the Future through Creative, Exciting Research

Ken Hansen, CEO
Semiconductor Research Corporation

In the history of the semiconductor industry, there has been no other period in time with as much uncertainty in the way forward. But with uncertainty comes great opportunity. There is a need for transformative innovation fueled by breakthrough research to reinvigorate the growth of the industry. This talk will identify some of the new exciting challenges the industry is facing and research areas where investment is needed address them. Systems of the future – autonomous vehicles, internet of things, self-adaptive configurations modeled on biology – will require advanced techniques to test them, secure them, reduce their power, and produce them without error. This increase in complexity coupled with a decreasing ability to rely on deterministic circuits requires new approaches to be created by cross-disciplinary teams co-optimizing across the entire design hierarchy space.

Bio: Ken Hansen joined Semiconductor Research Corporation as its President and CEO in June 2015. Ken brings his experience as the former Vice President and Chief Technology Officer with Freescale Semiconductor. Prior to becoming CTO at Freescale, Ken was Vice President and led Freescale’s Chief Development Office where he improved design efficiency and reduced product cost for all Freescale business units. Previously, he held several senior technology and management positions at Freescale and Motorola leading research and development teams. He received the BSEE and MSEE degrees from the University of Illinois where he also has been recognized as an ECE and College of Engineering Distinguished Alumni, is a Fellow of the IEEE, and holds 11 U.S. patents. Ken is an industry veteran, with 40 years of experience in technical management and system/circuit design, primarily in the area of wireless communications.



13:30-15:00 Session 17: Mixed-signal
Leroy Winemberg (NXP Semiconductor, USA)
Rubin Parekhji (Texas Instruments (Bangalore), India)
Stephen Sunter (Mentor Graphics, Canada)
Alessandro Valerio (STMicroelectronics, Italy)
Riccardo Miglierina (STMicroelectronics, Italy)
Automated Measurement of Defect Tolerance in Mixed-Signal ICs

ABSTRACT. Defect tolerance can improve system reliability and safety, or IC yield.  This paper describes how an analog fault simulator can measure defect tolerance of any analog, mixed-signal, or non-scan digital circuit within an IC.

Anthony Coyette (KU Leuven, Belgium)
Baris Esen (KU Leuven, Belgium)
Wim Dobbelaere (ON Semiconductor, Belgium)
Ronny Vanhooren (ON Semiconductor, Belgium)
Georges Gielen (KU Leuven, Belgium)
Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis

ABSTRACT. A method is presented to automatically generate test signals targeting specified faults in mixed-signal circuits. The proposed scheme mimics digital ATPGs and consists of a fault activation, backtracing and propagation mechanisms based on interval analysis.

Barry Muldrey (Georgia Institute of Technology, USA)
Sabyasachi Deyati (Georgia Institute of Technology, USA)
Abhijit Chatterjee (Georgia Institute of Technology, USA)
DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
SPEAKER: Barry Muldrey

ABSTRACT. Iterative and alternate on-the-fly test generation and least-squares fitting of embedded non-linear filters for circuit diagnosis predictions not requiring assumptions about the nature of faults.

13:30-15:00 Session 18: Practices
Peter Maxwell (ON Semiconductor, USA)
Yan Pan (Globalfoundries us Inc, USA)
Rao Desineni (Globalfoundries us Inc, USA)
Kannan Sekar (Globalfoundries us Inc, USA)
Atul Chittora (Globalfoundries us Inc, USA)
Sherwin Fernandes (Globalfoundries us Inc, USA)
Neerja Bawaskar (Globalfoundries us Inc, USA)
John Carulli (Globalfoundries us Inc, USA)
Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure

ABSTRACT. This paper describes a volume diagnosis infrastructure built on open-source software, which addresses practical challenges in a foundry environment by integrating various data sources from design, manufacturing process and test to enable rapid root-cause identification.

V.R. Devanathan (Texas Instruments Inc, USA)
Sumant Kale (Texas Instruments Inc, USA)
A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath

ABSTRACT. A reconfigurable memory self-repair architecture along with power and timing-aware synthesis flows, that support multiple IPs with diverse embedded BIST implementations, is presented. Experimental results on industrial designs indicate significant reductions in area and test-time.

Michael Johnson (IBM, USA)
Brian Noble (IBM, USA)
Cynthia Manya (IBM, USA)
John Deforge (IBM, USA)
Mark Johnson (IBM, USA)
James Crafts (IBM, USA)
Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring

ABSTRACT. Monitoring extrinsic defects on every die for every product in a technology is crucial to a robust reliability strategy. We demonstrate a low cost high efficiency system, the Active Reliability Monitor, which accomplishes this goal.

13:30-15:00 Session P4: Panel: ATE Revisited–Where Are We Today and Where Should We Be Heading?

Organizer: Bruce Parnas, Applied Materials

Every few years industry trends drive changes in the requirements for test equipment. This panel will look at trends in the last five years and the impact on ATE as well as look into the future.


Paul Berndt, Cypress Semiconductor

Holger Engelhard, Advantest

Qi Fan, Huawei

Ken Lanier,Teradyne

John Shelley, XCerra

Bruce Parnas (Applied Materials, USA)
Bob Bartlett (Advantest Corporation, USA)
13:30-15:00 Session P5: Panel: Test, Validation, and Security for IoTs

Organizer: Mark M. Tehranipoor, University of Florida

Abstract: IoTs are expected to be pervasive in home, businesses, smart communities and cities. IoT devices are now found in commonplace amenities such as cars, phones, watches, appliances, home and business security systems, thermostats, smoke detectors, as well as applications such as utilities, banking, transportation, energy, and (bio)medical industry. The number of devices introduced in the market as IoT has increased drastically, with an estimated 50 billion by 2020, most of which are expected to be fabricated off-shore.

The massive deployment of IoT devices and the shortened time-to-market has led to significant challenges including (i) testing, (ii) validation, and (iii) security and privacy concerns. This has left devices with many unintentional bugs and security vulnerabilities, which can cause data leakage, denial of service, and malicious modification of devices physically and/or remotely. The panelists will discuss the challenges that comes with such large scale growth of IoT devices in terms of test and validation. Further, end-to-end authentication from device-to-system, especially throughout the modern complex supply chain is also discussed.


Yousef Iskandar, Cisco, Confirmed

Michael Schuldenfrei, Optimal +, Confirmed

Michal Vai, MIT Lincoln Lab, Confirmed

Yervant Zorian, Synopsys, Confirmed





Mark Tehranipoor (University of Florida, USA)
Mark Tehranipoor (University of Florida, USA)
13:30-15:00 Session TUT2: Embedded Tutorial on ISO-26262

An introduction and overview of the ISO 26262 standard’s scope, the functional safety lifecycle concept, the requirements for safety integrity, hardware verification, hardware metrics and system safety integration verification.  Intended for engineers and managers involved in development of vehicle safety-related components and systems.

Ken Butler (Texas Instruments, USA)
David Tatman (Texas Instruments, USA)
Overview of the Automotive Functional Safety Standard ISO 26262 - Part I Design Impact
SPEAKER: David Tatman
Shrenik Mehta (Synopsys, USA)
Overview of the Automotive Functional Safety Standard ISO 26262 - Part II Tools and Methods
SPEAKER: Shrenik Mehta