EPEPS 2025: 34TH IEEE CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS

This page contains an index consisting of author-provided keywords.

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1.3DIC	A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs
2
2.Diffusion	A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs
3
3-D differential surface admittance (DSA) operator	Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures
3.thermal	A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs
4
4.sample-efficiency	A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs
448 Gbps	Package Technology Exploration for 448 Gbps Electrical Signaling
5
5.floorplanning	A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs
5G	Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction
A
Activation Function	Trainable Activation Functions with Applications in the Design of 3D Electromagnetic Structures
Active interposer	High-Bandwidth Memory (HBM) Network Switch Architecture Design with Low Latency and Efficient Energy Consumption for HBM Centric Computing
Adaptive Frequency Sampling	An Improved Adaptive Frequency Sampling Approach using Query by Committee
aging	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
AI	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach
AI	Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge
ai hardware	High-speed Interconnect Design for next-gen AI Hardware
analog signal processing	On-Chip Passive Dispersive Delay Lines for RF Chirp Pulse Shaping
applications	Augmented Reality Applications and Power Electronics Challenges
artificial intelligence	Stochastic S-Parameter Generation Using Denoising Regression for High-Speed Link Design Empowering Engineers, Enabling Innovation: The AI Journey
atomchip	Technology Demonstrator for a Glass-Based Quantum System
augmented intelligence	Empowering Engineers, Enabling Innovation: The AI Journey
augmented reality	Augmented Reality Applications and Power Electronics Challenges
B
backdrill	Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills
Backside power delivery network	Reinforcement Learning-Based Co-Optimization of Power and Thermal Integrity in Backside Power Delivery Network-Enabled Advanced Packages
balanced line	Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission
balanced line	Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing
bandit algorithm	Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
Bayesian neural networks	Machine Learning Framework for System-Level Prediction of Co-Packaged Optics
Bayesian optimization	Machine Learning Framework for System-Level Prediction of Co-Packaged Optics ADAPT - Adaptive Droop and Performance Tuner for Droop Mitigation Schemes
bent differential transmission lines	Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills
BEOL integration	Enhanced Thermal Conductivity of Electrodeposited Graphene-Cu Thin Films for BEOL Integration
BGA	Package Technology Exploration for 448 Gbps Electrical Signaling
BGA pin field	Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout
BiCGSTAB Solver	Optimized GPU Accelerated Computing Using FP32 for 3D Laguerre-FDTD Method
boundary element methods	A Multiresolution Preconditioner for the Electromagnetic Analysis of Large Interconnects
bridged-T coil	On-Chip Tunable Delay Line Using Complementary Bridged T-Coils with Inductor-Capacitor Tuning
broadside-coupled stripline	Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout
BSIM-CMG compact model	Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
burn in	Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach
C
calibration	Impulse-Response De-Embedding Correction For Non-Identical Fixturing
Cavity	Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
Channel-identification	High-Speed Channel Identification Using Contrastive Learning
Chiplet	Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad
Chiplet	Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
circuit simulation	Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
Clocking	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
CMR filter	Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission
Co-packaged optical systems	Machine Learning Framework for System-Level Prediction of Co-Packaged Optics
Co-packaged Optics	Machine-Learning-Based Optical I/O Design and Analysis Automation for Co-Packaged Optics
common-mode rejection	Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission
common-mode rejection	Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing
Computer-Aided Design	Trainable Activation Functions with Applications in the Design of 3D Electromagnetic Structures Towards Estimation of Worst-case Voltage Droop in Nonlinear Power Delivery Networks
Connectors	Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction
Contrastive learning	High-Speed Channel Identification Using Contrastive Learning
CPO	Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC
crosstalk	PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction Through-Plane Forward Crosstalk in Superconducting Stripline Transmission Lines Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
Crosstalk	Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
Cryogenic Measurements	Temperature Effects on Cryogenic Test Fixture Interconnects
Cryostats	Temperature Effects on Cryogenic Test Fixture Interconnects
CTLE	SPICE Based Optimization of Equalization in Channel Simulation
CUDA	Optimized GPU Accelerated Computing Using FP32 for 3D Laguerre-FDTD Method
D
DDR5	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
de-embed	Impulse-Response De-Embedding Correction For Non-Identical Fixturing
Decoupling capacitor	Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy
deep neural networks	Machine Learning Framework for System-Level Prediction of Co-Packaged Optics
Denoising regression	Stochastic S-Parameter Generation Using Denoising Regression for High-Speed Link Design
Design Optimization	Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
DFB laser	Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC
DFE	SPICE Based Optimization of Equalization in Channel Simulation
differential-to-common-mode conversion	Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills
digital signal	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels
DIMM	Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems
dispersive group delay	On-Chip Passive Dispersive Delay Lines for RF Chirp Pulse Shaping
Domain Decomposition	Waveguiding Approach to Via Design with Bandwidth over 120 GHz
DRAM	Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems
Droop Mitigation	ADAPT - Adaptive Droop and Performance Tuner for Droop Mitigation Schemes
Dual-encoder	High-Speed Channel Identification Using Contrastive Learning
Dynamic Time Warping	An Improved Adaptive Frequency Sampling Approach using Query by Committee
E
edge-coupled stripline	Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout
EDSFF Connector	Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
electrical	Electrical and Thermal Integrity in Interconnect Design: challenges and new opportunities
electromagnetic analysis	A Multiresolution Preconditioner for the Electromagnetic Analysis of Large Interconnects
Electromagnetic coupling	Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems
Electromagnetic Modeling	Waveguiding Approach to Via Design with Bandwidth over 120 GHz
Electromagnetic Simulation	An Improved Adaptive Frequency Sampling Approach using Query by Committee
EM Modeling	Trainable Activation Functions with Applications in the Design of 3D Electromagnetic Structures
end-to-end design	Empowering Engineers, Enabling Innovation: The AI Journey
Equalization	SPICE Based Optimization of Equalization in Channel Simulation Digital equalization for Multilevel signaling in high-speed SerDes
equivalent circuit	Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit
ethernet	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
F
fabrication	Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit
Fast iterative solvers	Efficient Hierarchical Skeleton-Based Low Rank Decomposition Technique for Integral Equations
fault-tolerance	`Spectral Harvesting': a Fault tolerant design technique for chip-scale interconnects
Feed-forward Equalizer (FFE)	Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
FFE	SPICE Based Optimization of Equalization in Channel Simulation
finite element method	Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC
fixture	Impulse-Response De-Embedding Correction For Non-Identical Fixturing
Frequency Domain Modeling	An Improved Adaptive Frequency Sampling Approach using Query by Committee
G
glass	Technology Demonstrator for a Glass-Based Quantum System
Glass substrate	Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge
glass weave	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels
GPU	Optimized GPU Accelerated Computing Using FP32 for 3D Laguerre-FDTD Method
graphene–copper films	Enhanced Thermal Conductivity of Electrodeposited Graphene-Cu Thin Films for BEOL Integration
gravimeter	Technology Demonstrator for a Glass-Based Quantum System
ground resonance	Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit
H
HBM	Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge
HBM-centric architecture	Power Integrity Design and Analysis of High Bandwidth Memory-centric Memory Pooling Computing Architecture
heat sink	Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach
heterogeneous integration	Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module High-speed Interconnect Design for next-gen AI Hardware
heterogenous I/O integration	Power Integrity Design and Analysis of High Bandwidth Memory-centric Memory Pooling Computing Architecture
High bandwidth memory	Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy
High bandwidth memory (HBM)	Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM
High performance computing (HPC)	Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
high pressure cooling	Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach
High-bandwidth memory	High-Bandwidth Memory (HBM) Network Switch Architecture Design with Low Latency and Efficient Energy Consumption for HBM Centric Computing
high-speed	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs Transceiver Architectures for Future System Interconnect Demands
high-speed digital signal	Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission
high-speed interconnects	Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout
High-speed link	Stochastic S-Parameter Generation Using Denoising Regression for High-Speed Link Design High-Speed Channel Identification Using Contrastive Learning
high-speed signaling	Package Technology Exploration for 448 Gbps Electrical Signaling
High-Speed Vias	Waveguiding Approach to Via Design with Bandwidth over 120 GHz
Hybrid bonding	Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad
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Impedance	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
impulse response correction	Impulse-Response De-Embedding Correction For Non-Identical Fixturing
insertion loss	Package Technology Exploration for 448 Gbps Electrical Signaling
integral equations	Tensor Train Acceleration of Volume Integral Equation Solutions for EM Analysis of Interconnects
Integrated circuits	Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems
Inter-Symbol Interference (ISI)	Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
interconnect	`Spectral Harvesting': a Fault tolerant design technique for chip-scale interconnects PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect Can a broken wire transmit signals?: Spoof Plasmonic Wires made of Metallic Islands High-speed Interconnect Design for next-gen AI Hardware Electrical and Thermal Integrity in Interconnect Design: challenges and new opportunities Transceiver Architectures for Future System Interconnect Demands
interposer	Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad
IO	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
L
Laguerre-FDTD	Optimized GPU Accelerated Computing Using FP32 for 3D Laguerre-FDTD Method
Latency insertion method	Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
leakage	Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
local polynomial interpolation	Temperature-Dependent SPICE Models for UCIe Interconnects
Local silicon bridge	Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge
logarithmic complexity	Tensor Train Accelerated Solution of Volume Integral Equation for 2D Magneto-Quasi-Static Characterization of Multiconductor Transmission Lines with Logarithmic Complexity
low-rank compression	Efficient Hierarchical Skeleton-Based Low Rank Decomposition Technique for Integral Equations
lower Dk	Package Technology Exploration for 448 Gbps Electrical Signaling
LPDDR5	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
Lumped-circuit model	High-Bandwidth Memory (HBM) Network Switch Architecture Design with Low Latency and Efficient Energy Consumption for HBM Centric Computing
LVR	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
M
machine learning	Machine Learning Framework for System-Level Prediction of Co-Packaged Optics Corner Modeling and Sensitivity Analysis of a Rough-Foil Microstrip using Machine Learning Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
Machine-Learning	Machine-Learning-Based Optical I/O Design and Analysis Automation for Co-Packaged Optics
Mamba	Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy
manufacturing	Technology Demonstrator for a Glass-Based Quantum System
material interfaces	Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures
MCP	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
measurement	Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit
Memory Architecture	Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems
Memory expansion	Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity
method of moments	Efficient Hierarchical Skeleton-Based Low Rank Decomposition Technique for Integral Equations Tensor Train Acceleration of Volume Integral Equation Solutions for EM Analysis of Interconnects
Microbump	Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad
MIP	Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems
mixed mode	Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
mode conversion	Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
Modeling	Towards Estimation of Worst-case Voltage Droop in Nonlinear Power Delivery Networks
multi-sleep modes	Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
N
negative-capacitance FinFET	Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
Neural Networks	Machine-Learning-Based Optical I/O Design and Analysis Automation for Co-Packaged Optics
O
on wafer	Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit
on-chip capacitor	Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures
on-chip delay unit	On-Chip Passive Dispersive Delay Lines for RF Chirp Pulse Shaping
On-chip interconnect	High-Bandwidth Memory (HBM) Network Switch Architecture Design with Low Latency and Efficient Energy Consumption for HBM Centric Computing
on-chip tunable delay line	On-Chip Tunable Delay Line Using Complementary Bridged T-Coils with Inductor-Capacitor Tuning
Optical I/O	Machine-Learning-Based Optical I/O Design and Analysis Automation for Co-Packaged Optics
organic core	Package Technology Exploration for 448 Gbps Electrical Signaling
OSFP	Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
P
package	Package Technology Exploration for 448 Gbps Electrical Signaling Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC
packaging	Technology Demonstrator for a Glass-Based Quantum System
PAM-4	PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
PAM4	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction
PCB	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
PCB material	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels
PCIe	PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
PCIe Gen6.0	Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
PHY	8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY
piecewise homogeneous media	Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures
Power Delivery Network	ADAPT - Adaptive Droop and Performance Tuner for Droop Mitigation Schemes
Power delivery network (PDN)	Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM
power delivery system	Vertical Power Delivery for High-Density Computing: Challenges and Opportunities
Power distribution network	Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy
power electronics	Augmented Reality Applications and Power Electronics Challenges
power gating	Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
power integrity	Towards Estimation of Worst-case Voltage Droop in Nonlinear Power Delivery Networks Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
Power integrity	Power Integrity Design and Analysis of High Bandwidth Memory-centric Memory Pooling Computing Architecture Reinforcement Learning-Based Co-Optimization of Power and Thermal Integrity in Backside Power Delivery Network-Enabled Advanced Packages
power integrity (PI)	Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM
printed circuit board	Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills
PSO	Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm
PTH	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
Q
quantum	Signal integrity Engineering With Superconductors: An Introduction
quantum systems	Technology Demonstrator for a Glass-Based Quantum System
quantum technology	Technology Demonstrator for a Glass-Based Quantum System
Query-by-Committee	An Improved Adaptive Frequency Sampling Approach using Query by Committee
R
Reinforcement learning	Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy Reinforcement Learning-Based Co-Optimization of Power and Thermal Integrity in Backside Power Delivery Network-Enabled Advanced Packages Bandit Learning-Driven Power Gating with State Retention for High Performance Computing
reliability	Can a broken wire transmit signals?: Spoof Plasmonic Wires made of Metallic Islands
resonance	Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
RL extractor	Tensor Train Accelerated Solution of Volume Integral Equation for 2D Magneto-Quasi-Static Characterization of Multiconductor Transmission Lines with Logarithmic Complexity
S
S-parameter	Stochastic S-Parameter Generation Using Denoising Regression for High-Speed Link Design
sensitivity	Corner Modeling and Sensitivity Analysis of a Rough-Foil Microstrip using Machine Learning
serdes	Package Technology Exploration for 448 Gbps Electrical Signaling SPICE Based Optimization of Equalization in Channel Simulation Digital equalization for Multilevel signaling in high-speed SerDes Transceiver Architectures for Future System Interconnect Demands
Servers	Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems
Settling Time	Temperature Effects on Cryogenic Test Fixture Interconnects
SI	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge
signal integrity	A Multiresolution Preconditioner for the Electromagnetic Analysis of Large Interconnects Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems Bandit Learning-Driven Power Gating with State Retention for High Performance Computing Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector
signal integrity	Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing
Signal integrity (SI)	Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces
signaling	Digital equalization for Multilevel signaling in high-speed SerDes
SignalIntegrity	SPICE Based Optimization of Equalization in Channel Simulation
silicon interposer	Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module
Simultaneous Switching Noise	Power Integrity Design and Analysis of High Bandwidth Memory-centric Memory Pooling Computing Architecture
single-source boundary integral equation (BIE)	Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures
SiP	Temperature-Dependent SPICE Models for UCIe Interconnects
skew	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels
spectral harvesting	`Spectral Harvesting': a Fault tolerant design technique for chip-scale interconnects
SPICE	SPICE Based Optimization of Equalization in Channel Simulation
Spoof-surface plasmon polariton	Can a broken wire transmit signals?: Spoof Plasmonic Wires made of Metallic Islands
SSD	PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect
Stateye	SPICE Based Optimization of Equalization in Channel Simulation
static IR drop	Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM
stripline	Through-Plane Forward Crosstalk in Superconducting Stripline Transmission Lines
superconductor	Through-Plane Forward Crosstalk in Superconducting Stripline Transmission Lines
superconductors	Signal integrity Engineering With Superconductors: An Introduction
surface roughness	Corner Modeling and Sensitivity Analysis of a Rough-Foil Microstrip using Machine Learning
surrogate modeling	Temperature-Dependent SPICE Models for UCIe Interconnects
switchable inductor	On-Chip Tunable Delay Line Using Complementary Bridged T-Coils with Inductor-Capacitor Tuning
T
TDP	Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach
TDR	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
tensor train	Tensor Train Acceleration of Volume Integral Equation Solutions for EM Analysis of Interconnects
Tensor train decomposition	Tensor Train Accelerated Solution of Volume Integral Equation for 2D Magneto-Quasi-Static Characterization of Multiconductor Transmission Lines with Logarithmic Complexity
testing	Technology Demonstrator for a Glass-Based Quantum System
thermal	Electrical and Thermal Integrity in Interconnect Design: challenges and new opportunities
thermal conductivity	Enhanced Thermal Conductivity of Electrodeposited Graphene-Cu Thin Films for BEOL Integration
Thermal integrity	Reinforcement Learning-Based Co-Optimization of Power and Thermal Integrity in Backside Power Delivery Network-Enabled Advanced Packages
through silicon via	Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module
through silicon via (TSV)	Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM
Through-silicon vias	Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems
time-domain gating	Impulse-Response De-Embedding Correction For Non-Identical Fixturing
tranceiver	Transceiver Architectures for Future System Interconnect Demands
transmission line	Through-Plane Forward Crosstalk in Superconducting Stripline Transmission Lines
Transmission Lines	Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction
TSV	Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC
tutorial	Vertical Power Delivery for High-Density Computing: Challenges and Opportunities Signal integrity Engineering With Superconductors: An Introduction Electrical and Thermal Integrity in Interconnect Design: challenges and new opportunities
Twinax cables	Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels
U
UCIe	Temperature-Dependent SPICE Models for UCIe Interconnects
ultra-high-speed digital signal	Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing
Universal Chiplet Interconnect Express	Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity
V
Vector Fitting	An Improved Adaptive Frequency Sampling Approach using Query by Committee
vertical power delivery	Vertical Power Delivery for High-Density Computing: Challenges and Opportunities
Via	SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs
via-to-trace crosstalk	Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout

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