ABSTRACT. The design of modern power delivery systems is at a turning point to enable future high performance computing systems and AI applications. Traditional high-voltage power converters, typically implemented on printed circuit boards (PCBs), have matured to efficiently deliver bulk power at the system level. In parallel, integrated voltage regulators (IVRs) have become essential for delivering fine-grain, low-noise power on-chip. Vertical power delivery (VPD) combines these two previously disjointed domains, creating a fundamentally new design paradigm that tightly integrates off-chip conversion efficiency with on-chip regulation fidelity. VPD collapses the hierarchical stack, bringing voltage regulation into the vertical die-stack proximity of high-performance ICs, and therefore demands innovation in circuits, devices, and co-design methodologies. As a result, the challenges traditionally addressed in separate communities—such as high-voltage device modeling, circuit-level noise resilience, in-situ control, and floorplan-aware delivery—must now be understood in a unified context. This convergence offers transformative opportunities, but also exposes gaps in existing design infrastructure, modeling, and abstraction. This tutorial will provide a system-to-device perspective on VPD and highlight open research challenges in achieving high-efficiency, high-density, and scalable power delivery. Topics will include distributed and stackable VPD architectures for ultra-high current (up to 50 kA) and high current density (2-4 A/mm2 on average and up to 10 A/mm² peak) targets, efficient conversion from high-voltage rails (e.g., 48V/12V-to-1V), and integrated power management across densely stacked heterogeneous systems. We will discuss hybrid voltage regulator design and opportunities for co-design across the vertical hierarchy. Emphasis will be placed on identifying methodological and modeling gaps and outlining promising directions toward systematic VPD implementation for next-generation heterogeneous platforms.

ABSTRACT. Multilevel signaling has extended the lifeline of wireline signaling beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophisticated equalization that is more suitable for digital implementation. This presentation aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-based solutions. Starting from traditional analog architectures, this talk will walk through the evolution toward today’s DSP-based equalization and provide the background for tomorrow’s sequence decoding.

ABSTRACT. Method of Moments (MoM) discretization of the Integral Equations (IEs) of electromagnetics results in dense matrix equation. Such matrix equations require prohibitively large computational resources when the number of basis functions used in discretization reaches hundreds of thousands and higher. Tensor Train (TT) decomposition of the MoM dense matrix equations has been recently proposed [1] to drastically reduce both the memory use for matrix storage and the CPU time required for its multiplication with a vector. Toeplitz matrix resulting from MoM discretization of Volume Integral Equation (VIE) can be represented as a multi-dimensional matrix and stored as a product of smaller dimensional matrices (tensors). Such product of smaller dimensional matrices, also known as the tensor train (TT), can reduce the matrix storage and matrix-vector multiplication complexities. In order to accelerate MoM solution of practical scattering problems we developed iterative Conjugate-Gradient- Tensor-Train (CG-TT) [2] and Precorrected-Tensor-Train (P-TT) [3] algorithms as well as direct AMEn-TT algorithm.

The CG-TT method works analogously with the well-established CG-FFT method [4]. Specifically, the VIE is MoM discretized with regular mesh of square elements and scattered field is cast into the form to discrete convolution. The Toeplitz matrix of the convolution is stored in TT-format. It is then used for fast evaluation of the pertinent matrix-vector products in the CG or GMRES iterative matrix solvers. To enable flexible meshing of the object with unstructured elements such as triangles, tetrahedrons, and others we developed the pre-corrected version of the algorithm. The latter projects onto a regular grid the basis and testing functions of the MoM defined on the unstructured elements similarly, with the Precorrected-FFT algorithm [5]. The point-to-point interactions forming the Toeplitz matrix are subsequently stored in the TT format, hence, enabling drastic reduction of memory and CPU time required for evaluation of the matrix-vector products during the iterative matrix solution.

In the non-iterative AMEn-TT algorithm we separately tensorize the Toeplitz matrix of interactions on the regular grid and the diagonal matrix describing spatial distribution of the material properties enabling definition of the arbitrarily shaped objects. The subsequent product of these matrices followed by the addition of the tensorized identity matrix produces resultant MoM matrix in TT format amenable to direct AMEn based solution.

Various numerical examples demonstrating O(logN) performance of the recently developed TT-based algorithms with over billion unknowns in the dense matrix equations resulting from full-wave MoM discretions of arbitrarily shaped geometries will be presented in this EPEPS Tutorial.

[1] I. V. Oseledets and E. Tyrtyshnikov, “TT-cross approximation for multidimensional arrays,” Linear Algebra and Its Applications, 432.1 (2010), pp. 70-88. [2] Z. Chen, S. Zheng, and V. Okhmatovski, “Tensor train accelerated solution of volume integral equation for 2D scattering problems and magneto-quasi-static characterization of multi-conductor transmission lines,” IEEE Trans. Microwave Theory Tech., vol. 67, no. 6, pp. 2181-2196, June 2019. [3] Z. Chen, L. Gomez, S. Zheng, A. Yucel, Z. Zhang, and V. Okhmatovski, “Sparsity-aware Precorrected Tensor Train algorithm for fast solution of 2-D scattering problems and current flow modeling on unstructured meshes,” EEE Trans. Microwave Theory Tech., vol. 67, no. 12, pp. 4833-4847, Dec. 2019. [4] M. F. Catedra, R. F. Torres, J. Basterrechea, and E. Gago, The CG-FFT Method: Application of Signal Processing Techniques to Electromagnetics, Boston, MA, Artech House, 1995. [5] J. R. Phillips and J. White, “A precorrected-FFT method for capacitance extraction of complicated 3-D structures,” Proc. Int. Conf. Computer-Aided Design (ICCAD), pp. 268 - 271, 1994.

ABSTRACT. Advancements in computing and high-speed wireless communications have led to the need for heterogeneously integrated packages and systems capable of higher throughput with lower energy consumption. This approach differs from previous methods that advanced each component individually and then integrated all necessary components onto system boards. Electronic package design is a significant aspect of the electronics industry. The current design paradigm emphasizes integrated chip-package co-design. This tutorial examines the crucial role of high-speed interconnect design in next-generation AI hardware, which facilitates efficient data transfer among processing units. As the computational demands of AI workloads continue to grow, it is imperative that interconnects deliver ultra-low latency, high bandwidth, and optimal energy efficiency. Emerging technologies—such as photonic interconnects, chiplet-based architectures, and high-speed SerDes—are integral to overcoming these challenges. The abstract discusses innovative design strategies, including coherent interconnect protocols and 3D integration, aimed at optimizing data movement within AI systems. By alleviating bottlenecks and improving scalability, these approaches support robust performance for large-scale AI models and contribute to significant advancements in machine learning and data processing. This course reviews advanced electrical design for packages and systems, focusing on signal and power integrity, codesign for improved reliability, and an overview of machine learning through system-level integration. Key topics include electronic packaging, heterogeneous integration, chip-to-chip signaling, and high-speed interconnect design. It addresses transmission line analysis and related challenges like delay, crosstalk, noise, and eye diagrams, concluding with the importance of chip-package co-design for system performance.

ABSTRACT. Superconductors are intriguing to signal integrity engineers. In contrast to normal conductors like copper that have resistance and thus both attenuation and dispersion, the zero resistance of superconducting interconnect often leads to visions of tremendous bandwidths over infinite physical distances. Superconductors are correspondingly finding their way into high-speed data links. While it is relatively easy to model the zero-resistance behavior of superconductors, doing so neglects unique properties of superconductors that directly impact signal integrity. In particular, a parameter unique to superconductors known as kinetic inductance affects characteristic impedance, propagation velocity, and crosstalk. Similarly, neglecting critical operating parameters such as temperature, field strength, and current can lead to disastrous results. Aimed at preparing engineers to analyze superconducting links, this tutorial introduces superconductors from the eyes of signal integrity engineers. It begins with an overview of the electrical behavior of superconductors and their critical operating parameters. Kinetic inductance and the associated London penetration depth are then introduced, followed by a selection of data link simulations to demonstrate the uniqueness of superconducting interconnect. Being targeted at practicing SI engineers, the tutorial omits the underlying physics of superconductors that are well covered in numerous textbooks. Prior experience with superconductors is unnecessary, but a general understanding of signal integrity is helpful.

ABSTRACT. Exascale computing for next generation AI data centers demands massive parallelism of integrated chips on package, with data-exchange among chips at terabyte-per-second (TB/s) bandwidth. This vision is severely constrained by two intertwined bottlenecks: i) limited bandwidth of the interconnect owing to their RC delay, and ii) thermal management challenges resulting from dense devices operating at high-speed. Ironically, approaches that reduce electrical losses often degrade thermal performance. For instance, porous, non-crystalline low-k substrates minimize parasitic capacitance, but their disordered structures and air pockets drastically reduce thermal conductivity. To navigate this complex scenario, it's essential for today's and future engineers to have a strong command of both electrical and thermal performance analysis techniques in electronic packaging. In the first half of this tutorial, we will discuss how key signal integrity metrics—such as propagation loss, crosstalk, and delay—relate directly to geometric features and material choices of interconnects. Concurrently, we will examine how thermal performance, including temperature profiles and hotspot generation, is also tied to interconnect design. This session will present how temperature, in turn, impacts interconnect performance through thermal noise, compromised conductivity, and long-term reliability, and how an equivalent electrical circuit model can be used for electrical and thermal co-design of interconnects. The second half of the tutorial will introduce an emerging alternative interconnect technology: electromagnetic surface-wave interconnects at a deep subwavelength scale. This technology employs engineered waveguides whose electrical transmission is optimized solely through metal interface engineering, allowing for independent selection and design of the bulk substrate for enhanced thermal performance. This decoupling of electrical and thermal optimization is a critical step toward ultra-high-speed computing. We will discuss techniques of designing and analyzing surface-wave interconnects, highlight the current status of this nascent technology and the key challenges that lie ahead for its integration into advanced packaging.