ABSTRACT. Augmented reality (AR) devices represent the next major leap in social technologies, poised to become the natural successor to the mobile internet. These devices promise to seamlessly blend the digital and physical worlds, enabling new forms of communication, collaboration, and interaction that are more immersive, context-aware, and intuitive than ever before. However, realizing this vision comes with significant technical challenges. Unlike smartphones, the glasses form factor must be lightweight, comfortable, and unobtrusive, all while supporting advanced features such as high-resolution displays, always-on sensors, and real-time connectivity. Achieving this requires breakthroughs in many technical fields, from optics and display, computer vision, memory technology, low-power silicon, system integration, and more. In this talk, we will delve into the specific power and integration-related hurdles facing the development of next-generation AR devices. Topics will include strategies for optimizing power consumption, challenges in AR interconnects, trade-offs between device form factor and battery life, and advances in power delivery systems needed to enable all-day wearable experiences. By addressing these challenges, we aim to pave the way for a future where augmented reality is as ubiquitous and essential as the mobile internet is today.

ABSTRACT. For the first time, this paper proposes a Mamba-based reinforcement learning (RL) method for high bandwidth memory (HBM) power distribution network (PDN) optimization. The proposed RL framework trains a probing port-agnostic policy using a Mamba architecture, which processes data sequences faster and more efficiently than the Transformer architecture with $\text{O(N)}$ linear computational complexity. For various probing port configurations and the number of decoupling capacitors (decaps), the proposed method is trained with the proximal policy optimization (PPO) algorithm to find the optimal positions to assign decaps on the PDN. The rewards are based on the suppression of both self- and transfer-impedance from 100 MHz to 30 GHz compared to the bare PDN. For verification, the proposed method is applied to the HBM4 2K I/O interface with unseen probing port configurations, demonstrating reusability. The trained policy achieves greater impedance suppression compared to the random search (RS) and genetic algorithm (GA) methods with a single inference and outperforms Transformer-based RL while reducing training time.

ABSTRACT. This paper presents an adaptive machine learning framework for co-packaged optics, integrating deep and Bayesian neural networks to enable performance prediction with uncertainty quantification. The approach achieves 96% accuracy, offering a scalable solution for photonic-electronic integration.

ABSTRACT. As semiconductor systems scale toward higher performance and density, advanced packaging technologies must address both power integrity (PI) and thermal integrity (TI) challenges. Backside power delivery network (BSPDN) architectures reduce IR drop and improve layout flexibility, but they exacerbate thermal issues due to die thinning and backside metallization, resulting in tightly coupled PI–TI trade-offs. This paper proposes a reinforcement learning (RL)-based framework for BSPDN-aware co-optimization of floorplan and decap configurations, formulated using a deep Q-network (DQN). BSPDN-specific physical models, including a compact thermal resistance matrix and layout-constrained decap placement, are integrated for fast and accurate evaluation. The proposed method achieves more than 3.1% improvement in a scalarized figure of merit (FoM) over single-objective baselines, with over 90% runtime reduction. These results validate the effectiveness of the framework for scalable PI/TI co-design in BSPDN-integrated systems.

ABSTRACT. Worst-case droop in nonlinear Power Delivery Networks is estimated by harnessing existing optimal control techniques with data-driven bilinear macromodels to find the worst-case stimulus. The approach is numerically demonstrated on a realistic Low-DropOut regulator.

ABSTRACT. In this paper, for the first time, we propose a denois- ing regression-based S-parameter generation method for high- speed channel design. The proposed model enables controlled, diverse and realistic synthesis of S-parameters conditioned on physical dimensions of given channel. During training, it learns a robust denoising regression mapping that captures global relationships between physical dimensions and frequency-domain responses. At generation time, a tunable latent scale factor modulates injected stochasticity, enabling controllable diversity that reflects unpredictable design variations. We experimentally demonstrate that this factor enables a trade-off between accurate prediction and diversity and shows robustness in S-parameter synthesis. As a result, it is effective for constructing large, high- quality S-parameter datasets for design validation.

ABSTRACT. FinFET technology has been steadily replacing the traditional MOSFET in sub-20 nm IC devices, due to its low power consumption and excellent scaling characteristics. However, scaling FinFETs beyond 3 nm is a challenging process. To pursue better power efficiency and performance, the negative capacitance FinFET (NC-FinFET) has been introduced by adding an extra ferroelectric layer at the gate. In this paper, we propose a fast simulation algorithm for NC-FinFETs based on the Latency Insertion Method (LIM). By integrating the BSIM-CMG model and the Landau-Khalatnikov Ferroelectric model, the proposed algorithm achieves orders of magnitude in speedup over conventional circuit simulators for large-scale examples.

ABSTRACT. Crosstalk becomes a growing challenge for high-speed serial links. This paper proposes to use the broadside-coupled stripline breakout to mitigate the via-to-trace coupling in the BGA pin field. Compared with the typical edge-coupled stripline breakout, the broadside-coupled escaping traces with one-pair or 2-pair routing schemes amid the differential via center demonstrate more than 40dB improvement in via-to-trace crosstalk. In addition, the impact by the inner layer misregistration is evaluated with the board fabrication tolerance. The time-domain PAM4 64Gbps channel simulations show significant eye openings, which validates the analyses of the full-wave models in the frequency domain.

ABSTRACT. As products using 224 Gbps per-lane serializer/deserializer (SerDes) electrical signaling speed are being introduced in industry, 448 Gbps is emerging as the next signaling speed target for Ethernet. This paper provides the results of an exploration study that aims to enable 448 Gbps electrical signaling through an electronic package. More specifically, technology recommendations for package build-up and second-level interconnect (SLI) technologies, along with preliminary validation data for some initial technology options will be presented. With the envisioned technology building blocks, we demonstrate that it will be feasible to achieve comparable level of electrical signaling performance for 448 Gbps for data center product packages as 224 Gbps.

ABSTRACT. Electromagnetic coupling between Through-Silicon Vias (TSVs) and adjacent metal wires in 2.5D interposer integrated chips (ICs) is a critical signal integrity (SI) concern for high-speed server systems. While TSV technology offers significant advantages such as shorter interconnect length, reduced power consumption, and faster speed; their close proximity to package metal wires introduces parasitic capacitance which can severely degrade the signal integrity to the point of eye closure. This paper presents numerical analysis and hardware measurement data of the impact of such parasitic coupling in high-speed computer circuits. Frequency as well as time domain results are reported to illustrate the importance of controlling the capacitive coupling between TSVs and routing wires using keep-out zone (KOZ) to ensure fast, reliable and robust computing system designs.

ABSTRACT. Advancements in AI and MCP technologies drive demands for thick PCBs with multiple-layers capable of routing high-speed signals. This work focuses on optimizing SI performance of high-speed PTH vias in thick PCB designs.

ABSTRACT. High-performance CPU/GPU/AI processors consume high power with aggressive load current changes (dI/dT) leading to large voltage droops in the power delivery network (PDN) and potential timing failures. Droop mitigation techniques using adaptive clock modulation are often adopted to address these issues. These methods compare supply noise to one or multiple voltage thresholds and modulate the clock to create relaxed dI/dT profiles. Due to PDN and load current (Icc(t)) interactions, entry and exit from modulated clock profiles follow specific sequences, such as staggered restore of the clock frequency, to balance performance and droop (power) saving. In this work, we propose an automated tuner tool that analyzes various optimization settings, generating the best droop mitigation configuration, saving engineering time and speeding up the design cycle.

ABSTRACT. The rise of AI workloads and growing data center demands have driven the need for ultra-high-speed interconnects exceeding 200 Gb/s. As unit intervals (UI) shrink, even a few picoseconds of P/N skew can degrade serializer-deserializer (SerDes) performance. Traditional methods for quantifying skew fall short in capturing its impact. We introduce two new metrics: 1) Skew-Induced Insertion Loss Deviation (SILD) and 2) its complementary Figure of Merit (\text{FOM\_SILD}), analytically developed to assess P/N skew effects. Measured S-parameters confirm \text{FOM\_SILD} reciprocity, while simulations of 224G PAM4 SerDes show strong correlation with bit error rate (BER) trends. This approach offers a robust framework for analyzing skew in next-generation ultra-high-speed interconnects.

ABSTRACT. In order to address the frequent failure of wires in high density semiconductor package, this work introduces `spectral harvesting', a novel technique that exploits the unutilized RF bands of adjacent functional wires to carry the data from failed ones. The architecture employs a default RF carrier frequency $\omega_0$ for healthy wires and an auxiliary frequency $\omega_F$ for failed wires, both using ASK modulation. A new passive, frequency-selective directional coupler is introduced, which allows the $\omega_F$ signal from a failed wire to spontaneously merge with the adjacent healthy wire's $\omega_0$ signal to flow concurrently. At the destination, $\omega_F$ spontaneously dissociates from $\omega_0$, thereby bypassing the failed wire. Both the coupler and architecture are validated via simulation and experimentation using ASK modulation at $\omega_0=0.33$ GHz, $\omega_F=2.4$ GHz carrier with $20$ KHz bitrate.

ABSTRACT. Peripheral Component Interconnect Express (PCIe) has emerged as a key technology in the AI and machine learning (ML) market due to its ability to support massively parallel computing demands at low cost while providing high bandwidth, low latency, low power consumption, and a reliable communication channel. Although the 128 GT/s signal transmission rate per lane of PCIe Gen 7.0 is still lower than the maximum speed of Ethernet, some might assume that adopting solutions such as optical cables used in Ethernet would pose minimal signal integrity (SI) risk. However, a dilemma arises because PCIe prioritizes cost efficiency, and we have verified that SI-robust designs are still achievable using conventional legacy interconnect technologies for Gen 7.0. In this paper, we propose design optimizations that were previously overlooked or dismissed in earlier PCIe generations under the pretext of the “gray zone,” along with a new compression-type connector for cost-effective copper (Cu)-based PCIe links. We demonstrate that design improvements in the gray zone, combined with the application of the new connector, can improve PAM-4 eye SI characteristics by approximately 85 % compared to the previous worst-case design.

ABSTRACT. This paper describes key features implemented in DDRPHY of Intel Core Ultra processors (MeteorLake/ ArrowLake) which achieves data-rates up to 8.4GTS for LPDDR5x and 6.4GTS for DDR5 with significant power optimizations. Novel clocking architecture uses 8 phase PLL and separate distribution for IO clocking with phase and duty cycle correction, and per lane Phase Interpolators (PI); this enables ~50% reduction of Transmitter (Tx) insertion delay and jitter with lower power. Linear voltage regulators (LVR) with adaptive zero generate three dynamic voltage and frequency scaling (DVFS) rails for analog, clocking and LPDDR5 Tx. Unstacked Tx with advanced aging mitigation and phase-based equalization reduces power. 8x16 PHY achieves 2.7pj/b at 6.4GTS in LPDDR mode, excluding LVR loss, with area of 6.6mm^2 in TSMC N6 process.

ABSTRACT. We present a systematic field diagnosis of mixed‑mode ground resonances on an OSFP connector up to 60 GHz for 212 Gbps applications. The analysis reveals the field‑behavior fingerprints of ground cavities and their effects on all mixed‑mode performances of multi‑pair OSFP, including differential‑to‑differential (DD), differential‑to‑common (DC), common‑to‑common (CC), and common‑to‑differential (CD) insertion loss (IL), return loss (RL), and near‑end and far‑end crosstalk (NEXT/FEXT).

ABSTRACT. In this paper, we introduce a novel approach to the design and optimization of PCB and packaging vias for high-speed applications with bandwidths over 120 GHz. We propose the design of any-stackup vias using waveguiding structures similar to substrate-integrated waveguides, specifically substrate-integrated coaxial (SICW) and twinax (SITW) waveguides. This design is further simplified by segmenting the vias into middle sections and transitions. Our analysis demonstrates that the middle sections of SICW and SITW are relatively independent of the stackup structure and insensitive to the number and location of reference planes. Our work provides a robust and simple methodology for designing vias that are less sensitive to manufacturing variations and stackup adjustments and suitable for bit rates up to 448 Gbps.

ABSTRACT. This paper, for the first time, analyzes the advanced package chiplet channel with hybrid-bonding pads. Chiplets channels through silicon interposer require very high bandwidth communication among dies for high performance. However, signal integrity issues limit the bandwidth between chiplets. Especially, due to high data rates, the effects of bumps on each side of interposer trace has become non-negligible. To mitigate the issue, hybrid bonding pad can be used instead of microbump to bond interposer and chiplet to lessen loss and crosstalk. Hence, this paper proposes a chiplet channel solution with hybrid bonding. Also, it further investigates the potential bandwidth that hybrid bonding structure can achieve. For verification, first, interposer trace structure is designed, considering the routability. Then, hybrid bonding array is added to each side of interposer trace for full-channel simulation in frequency and time domain. We verified that for interposer trace, ground shielding is required between signal traces to meet the crosstalk specification. Also, replacing microbumps with hybrid bonding pads decreases the loss and crosstalk by 0.4 dB and 2.6 dB, which leads to maximum bandwidth increase of 16.5%.

ABSTRACT. Multilayer superconducting processes have enabled the construction of VLSI superconducting logic circuits. The length of superconducting passive transmission lines (PTL) in such processes are not limited by loss, therefore it becomes possible for long coupled sections of PTL to exist even in fine-pitch designs. Forward crosstalk (FXT) magnitude between coupled PTLs is proportional to coupled length, opening the possibility of significant FXT between long superconducting traces. Traditionally, signal integrity (SI) engineers constrain PTL layout to mitigate FXT between nearby in-plane features. However, inductive coupling also exists between PTLs located on different integrated circuit (IC) routing layers, even those separated by shielding ground planes. FXT between such structures can become problematic if coupling length is not constrained in layout. In this paper we explore through simulation FXT as a function of coupled length, London penetration depth, and offset between PTLs. We show that coupled lengths as low as 1 mm have greater than -40 dB of FXT through a shielding ground plane in a representative superconducting fabrication process.

ABSTRACT. As artificial intelligence (AI) and high-performance computing (HPC) applications continue to advance, chips with extremely high power consumption present growing challenges in thermal management. This study demonstrates that the Massive-Airflow-Cooling Heat Sink (MAC-HS) system significantly improves thermal performance under high-pressure conditions. Experimentally, it achieved 1580 W of heat dissipation with a thermal resistance of 0.047 °C/W at 4 atm. Simulation results further indicate that the system can handle up to 2000 W at 6 atm while maintaining junction temperatures below critical limits. These findings confirm MAC-HS as a reliable and scalable alternative to liquid cooling for high-power applications.

ABSTRACT. An ultra-wideband common-mode rejection filter structure with autonomous phase/amplitude balancing, consisting of a balanced line and L-/T-shaped conductor strips, is presented. The proposed filter demonstrates 10 dB level of common-mode rejection from 11.1 GHz to 40 GHz.

ABSTRACT. A compact signal integrity recovery module with a CPS-based signal balancing structure is proposed. The proposed module demonstrates rejection of common-mode noise and restoration of signal imbalance from 11.4 GHz to over 20 GHz.

ABSTRACT. Co-packaged optics (CPO) has emerged as a promising solution by integrating photonic components, such as distributed feedback (DFB) lasers, with electronic integrated circuits (EIC) on a single substrate. However, the thermal stress induced by mismatched coefficients of thermal expansion (CTE) among materials presents reliability challenges. This study proposes a novel CPO architecture that incorporates a DFB laser and EIC and evaluates its mechanical reliability through the finite element method. Various structural parameters were optimized, including microbump materials, bottom interposer thickness, and through-silicon-via (TSV) diameter in the bottom interposer. These findings provide valuable insights into enhancing the mechanical integrity and reliability of next-generation CPO systems.

ABSTRACT. We report Gr–Cu thin films with >600 W/m·K thermal conductivity and low resistivity, electrochemically deposited on silicon. The films meet BEOL roughness specs, offering a scalable route to high-performance interconnects.

ABSTRACT. For high speed applications such as SerDes [1], equalization techniques are used extensively to improve the eye diagram and Bit Error Rate. Common equalization techniques used are FFE (Feed Forward Equalization), CTLE (Continuous Time Linear Equalization), and DFE (Decision Feedback Equal- ization). The choice of equalization parameters depends on the channel. This paper provides a SPICE based methodology for optimizing the parameters for FFE, CTLE, and DFE for a given channel. The pulse response, obtained from SPICE, is used. As it is SPICE based, almost any circuit element can be handled.

ABSTRACT. A novel method for suppressing differential-to-common-mode conversion on bent differential transmission lines using backdrills is proposed. In contrast to conventional methods that require design changes or additional components, the proposed method can be implemented after fabrication on existing PCBs by applying backdrilling. The method employs parametric optimization of drill diameter and drill hole count using ANSYS Q3D simulations to maximize the phase velocity difference between the differential lines. The design with optimized backdrills maintains a 180° phase difference from DC–15 GHz, effectively suppressing differential-to-common-mode conversion. The simulated results validate the optimal backdrill configuration enhancing the signal integrity of the system, confirming the method’s efficacy in suppressing differential-to-common-mode conversion.

ABSTRACT. To address mechanical and electrical failures in advanced semiconductor packaging, this work introduces electromagnetically engineered wire, supporting spoof surface plasmon polariton (SSPP) mode that can remain functional even after electrical discontinuities. The proposed structure consists of a periodic metal-islands connected by metallic bridges. The odd-symmetric SSPP mode is shown to be resilient to multiple electrical discontinuities along the wire with no apparent change in transmission spectrum. The transmission efficiency of the odd-mode reaches as high as $-0.9$ dB for lossless substrate with a FWHM exceeding $1.9$ GHz. The prediction from simulation is validated by experimental measurement of $125$ mm long engineered wire on FR4 substrate within $6.5$ GHz transmission window.

ABSTRACT. As data center and AI applications drive the need for high-bandwidth and high-capacity memory modules, new ways to build traditional DRAM DIMM need to be studied. This paper looks at the use of direct attachment of DRAM die to the “PCB-like” packages utilizing finer geometries and improved design rules to increase channel bandwidth and memory densities.

ABSTRACT. Full wave 3D electromagnetic (EM) solvers are computationally expensive for applications that require dense frequency samples. Adaptive Frequency Sampling (AFS) is used to ease this burden. However, the use of traditional AFS algorithms may suffer from inaccuracy arising from false convergence and high runtime due to suboptimal next frequency selection. Further, the serial nature of AFS limits the scalability. This paper introduces Query by Committee (QBC) based AFS framework that uses a diverse set of models for improved decision making in next frequency point selection. This method is compared against conventional algorithms across different test cases. The Dynamic Time Warping (DTW) error scheme that measures the similarity between two data sequences is used to measure accuracy between S-parameters resulting from AFS and Discrete Frequency Sampling (DFS).

ABSTRACT. This paper proposes a Quad Tower High Bandwidth Memory (QT-HBM) architecture integrating four DRAM stacks on a unified base die using a glass substrate and local silicon bridges. This design addresses the scalability and signal integrity limitations of conventional silicon interposers for next-generation AI workloads. QT-HBM achieves 100% higher memory capacity, 80% greater total bandwidth, and 36% improved memory density over conventional HBM4 modules. Electromagnetic simulations confirm compliance with JEDEC standards at 7.2Gb/s, supporting its suitability for high-performance AI systems.