Vertical Power Delivery for High-Density Computing: Challenges and Opportunities (abstract)

Digital equalization for Multilevel signaling in high-speed SerDes (abstract)

Tensor Train Acceleration of Volume Integral Equation Solutions for EM Analysis of Interconnects (abstract)

High-speed Interconnect Design for next-gen AI Hardware (abstract)

Signal integrity Engineering With Superconductors: An Introduction (abstract)

Electrical and Thermal Integrity in Interconnect Design: challenges and new opportunities (abstract)

Augmented Reality Applications and Power Electronics Challenges (abstract)

Mamba-based Reinforcement Learning Method for HBM Power Distribution Network (PDN) Optimization with Probing Port-Agnostic Policy (abstract)

Machine Learning Framework for System-Level Prediction of Co-Packaged Optics (abstract)

Reinforcement Learning-Based Co-Optimization of Power and Thermal Integrity in Backside Power Delivery Network-Enabled Advanced Packages (abstract)

Towards Estimation of Worst-case Voltage Droop in Nonlinear Power Delivery Networks (abstract)

Stochastic S-Parameter Generation Using Denoising Regression for High-Speed Link Design (abstract)

Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method (abstract)

Via-to-Trace Crosstalk Mitigation in the BGA Pin Field With the Broadside-Coupled Breakout (abstract)

Package Technology Exploration for 448 Gbps Electrical Signaling (abstract)

Signal Integrity Analysis of Parasitic Coupling between Through Silicon Vias and Metal Wires in High-Speed Server Systems (abstract)

SI Performance Optimization on High-Speed Plated-Through-Hole Vias for AI and MCP-Driven Designs (abstract)

ADAPT - Adaptive Droop and Performance Tuner for Droop Mitigation Schemes (abstract)

Skew-Induced Insertion Loss Deviation (SILD) and FOM_SILD: Metrics for Quantifying P/N Skew Effects in High-Speed Channels (abstract)

`Spectral Harvesting': a Fault tolerant design technique for chip-scale interconnects (abstract)

PCIe Gen 7.0 System-level Design Considerations for Conventional Cu-based Interconnect (abstract)

8.4GTS LPDDR5x and 6.4GTS DDR5 Combo PHY (abstract)

Systematic Diagnosis on Mixed-Mode Resonances up to 60 GHz for 212.5 Gbps OSFP Connector (abstract)

Waveguiding Approach to Via Design with Bandwidth over 120 GHz (abstract)

Signal Integrity Analysis of Chiplet Channel With Interposer Trace and Hybrid Bonding Pad (abstract)

Through-Plane Forward Crosstalk in Superconducting Stripline Transmission Lines (abstract)

Heat Dissipation Characteristics of Massive Airflow Cooling Heat Sinks: A High-Pressure Air-Surrounded Approach (abstract)

Ultra-wideband Common-mode Rejection Filter Structure with L- and T-shaped Patterns for Ultra-High-Speed Data Transmission (abstract)

Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing (abstract)

Optimization of Co-Packaged Optics (CPO) Layout with Integrated DFB Laser and EIC (abstract)

Enhanced Thermal Conductivity of Electrodeposited Graphene-Cu Thin Films for BEOL Integration (abstract)

SPICE Based Optimization of Equalization in Channel Simulation (abstract)

Suppressing Differential-to-Common-Mode Conversion on Bent Differential Transmission Lines using Backdrills (abstract)

Can a broken wire transmit signals?: Spoof Plasmonic Wires made of Metallic Islands (abstract)

Direct Die Attached on PCB-like large packages for High Bandwidth AI-Memory Systems (abstract)

An Improved Adaptive Frequency Sampling Approach using Query by Committee (abstract)

Quad Tower High Bandwidth Memory (QT-HBM) with Glass Substrate and Local Silicon Bridge (abstract)

Empowering Engineers, Enabling Innovation: The AI Journey (abstract)

Crosstalk-Aware MMSE Equalizer Design for Chiplet Interfaces (abstract)

Temperature-Dependent SPICE Models for UCIe Interconnects (abstract)

Signal Integrity Design and Analysis of Inter-Stack Crosslink for 3D-Heterogeneous Integrated High Bandwidth Memory (3D-HI-HBM) Module (abstract)

Ground Resonance On-Wafer Measurement up to 67 GHz and Modeling with Physical Equivalent Circuit (abstract)

Separate-Cavity Optimization Method for PCIe Gen6.0 PCB-Connector Pad Design Using Particle Swarm Optimization (PSO) Algorithm (abstract)

A Conditional Diffusion Framework for Sample-Efficient Thermal Modeling in 3DICs (abstract)

Machine-Learning-Based Optical I/O Design and Analysis Automation for Co-Packaged Optics (abstract)

High-Speed Channel Identification Using Contrastive Learning (abstract)

Multimode Phase-Matching Technique for 128 GT/s PAM4 PCIe Connector Resonance Reduction (abstract)

Corner Modeling and Sensitivity Analysis of a Rough-Foil Microstrip using Machine Learning (abstract)

High-Bandwidth Memory (HBM) Network Switch Architecture Design with Low Latency and Efficient Energy Consumption for HBM Centric Computing (abstract)

Design and Analysis of Scalable On-Package Memory Expansion Architectures for GPU-HBM System Considering Signal Integrity (abstract)

Design and Analysis of Power/Ground TSVs considering Static IR Drop for Next-generation HBM (abstract)

Power Integrity Design and Analysis of High Bandwidth Memory-centric Memory Pooling Computing Architecture (abstract)

Transceiver Architectures for Future System Interconnect Demands (abstract)

Optimized GPU Accelerated Computing Using FP32 for 3D Laguerre-FDTD Method (abstract)

A Multiresolution Preconditioner for the Electromagnetic Analysis of Large Interconnects (abstract)

Trainable Activation Functions with Applications in the Design of 3D Electromagnetic Structures (abstract)

Broadband Impedance Response Extraction of On-Chip Interdigital Capacitors using a 3-D DSA Operator for Piecewise Homogeneous Structures (abstract)

Efficient Hierarchical Skeleton-Based Low Rank Decomposition Technique for Integral Equations (abstract)

Tensor Train Accelerated Solution of Volume Integral Equation for 2D Magneto-Quasi-Static Characterization of Multiconductor Transmission Lines with Logarithmic Complexity (abstract)

Bandit Learning-Driven Power Gating with State Retention for High Performance Computing (abstract)

Technology Demonstrator for a Glass-Based Quantum System (abstract)

Temperature Effects on Cryogenic Test Fixture Interconnects (abstract)

On-Chip Passive Dispersive Delay Lines for RF Chirp Pulse Shaping (abstract)

On-Chip Tunable Delay Line Using Complementary Bridged T-Coils with Inductor-Capacitor Tuning (abstract)

Impulse-Response De-Embedding Correction For Non-Identical Fixturing (abstract)