ITC 2017: INTERNATIONAL TEST CONFERENCE 2017

This page contains an index consisting of author-provided keywords.

1
1149.1	Quo Vadis IJTAG.1?
1687.1	Quo Vadis IJTAG.1?
3
3D Design for Test	Analytical Test of 3D Integrated Circuits
3D IC test	Testing TSVs for Micro-void and Pinhole Defects Using OTA
3D/2.5D Test	Analytical Test of 3D Integrated Circuits
A
adaptability	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Adaptive voltage scaling	Transition Fault Testing for Offline Adaptive Voltage Scaling
ADC	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
ADC testing	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter
advanced board test	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
alternate tests	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Analog	Thwarting Analog IC Piracy via Combinational Locking
analog DFT	Single-Pin Test Control for Big A, little d Devices
analog fault model	A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
Analog test	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Analog-to-Digital Converter	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
Analogue Test Bus	Use Models for Extending IEEE 1687 to Analog Test
Analytical Test	Analytical Test of 3D Integrated Circuits
analytics	Taming of the Shmoo
Anomaly detection	Run-Time Hardware Trojan Detection Using Performance Counters Changepoint-based Anomaly Detection in a Core Router System
APDL	Use Models for Extending IEEE 1687 to Analog Test
aperture jitter	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
assembled PCB test	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Asymmetric DJ Model	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
At-speed Test	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
ATE	Use Models for Extending IEEE 1687 to Analog Test Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
ATPG	On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode
Automatic test pattern generation	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
Automation	Use Models for Extending IEEE 1687 to Analog Test Automated Die Inking: A Pattern Recognition-based Approach
Automotive electronics test	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Automotive parts	Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Automotive self-test	A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test
B
benchmark	A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
BER	Self-Test and Self-Repair Method for FPGAs
BIST	BIST On-demand Using Distributed On-Chip Programmable Data Streams An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Bit Error Rate (BER) Curve Estimation	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
bit-error rate	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
bounded model checking	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
bridge fault	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
bridging faults	Selecting Target Bridging Faults for Uniform Circuit Coverage
broadside tests	POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits
built-in self-repair (BISR)	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Built-in Self-Test	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
built-in self-test (BIST)	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Built-In-Self-Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams
C
Calibration	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
changepoint detection	Changepoint-based Anomaly Detection in a Core Router System
Clock Domain aware test	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
Clock Grouping	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
clock jitter	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
Clock Sequencing	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
Clock Skew	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
cluster commonality	Kernel-based Clustering for Quality Improvement and Excursion Detection
cluster detection	Kernel-based Clustering for Quality Improvement and Excursion Detection
COGO	Multisite PMIC Fast Trimming with Pattern-based Search Function
Cold Test Elimination	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
comparator network	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
Compressed Production test set	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
Concolic execution	RTL Functional Test Generation Using Factored Concolic Execution
controllability	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Convolution Compressor	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
core router system	Symbol-based Health-Status Analysis in a Core Router System Changepoint-based Anomaly Detection in a Core Router System
Cost Of Test	Delay Fault Testing Using Cloud Testing Service
critical area	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
Cross-correlation	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
crosstalk	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
Customer return	Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Cycle-accurate simulation	RTL Functional Test Generation Using Factored Concolic Execution
D
Data Analysis	Taming of the Shmoo
data converter	Accurate ADC Testing with Significantly Relaxed Instrumentation Including Large Cumulative Jitter
data driven	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
data mining	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
data retention	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Data-Parallel Timing Simulation	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Defect based test for analog
defect diagnosis	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
defect level	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
Defect screening	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
defect-oriented test	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
Delay correlation	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
Delay Fault Testing	Delay Fault Testing Using Cloud Testing Service
delay faults	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
delay test	Multicycle At-Speed Test
delay test coverage	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
Design for manufacturability	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
design for test	A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
Deterministic Jitter (DJ)	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
DFT	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode Advancing Test Compression to the Physical Dimension
DRAM refresh	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
DRAM reliability	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
Dual-edge Triggered Flip-flop	On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops
dynamic errors	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
E
EDT	Hierarchical Hybrid EDT-LBIST System
embedded clock	Single-Pin Test Control for Big A, little d Devices
embedded instruments	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
embedded statistics	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
energy efficiency	Cross-Layer Refresh Mitigation for Efficient and Reliable DRAM Systems: A Comparative Study
error tolerance	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
F
Fast Trim	Multisite PMIC Fast Trimming with Pattern-based Search Function
fault diagnosis	Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects
fault isolation	Taming of the Shmoo Self-Test and Self-Repair Method for FPGAs
fault model	Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
fault simulation	High-Throughput Multiple Device Diagnosis System Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects
flat physical layout	Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study
FPGA	Self-Test and Self-Repair Method for FPGAs Interstitial DFT in SpeedCore™
Free Running Clock	Delay Fault Testing Using Cloud Testing Service
Fucntional Test Generation	RTL Functional Test Generation Using Factored Concolic Execution
functional test	Multicycle At-Speed Test
G
GPGPU	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
H
Hardware Security	Hardware Trojan Detection Through Information Flow Security Verification
Hardware Trojan	Hardware Trojan Detection Through Information Flow Security Verification
Hardware Trojans	Run-Time Hardware Trojan Detection Using Performance Counters
Hierarchical	Hierarchical Hybrid EDT-LBIST System
hierarchical clustering	Symbol-based Health-Status Analysis in a Core Router System
hierarchical designs	Technique to Test Hierarchical Designs with Multiple Design Levels
hierarchical DFT methodology	Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study
High resolution ADC testing	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
high speed data links	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
I
IC piracy	Thwarting Analog IC Piracy via Combinational Locking
ICL	Quo Vadis IJTAG.1?
ICL/PDL	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
IEEE 1149.1	BIST On-demand Using Distributed On-Chip Programmable Data Streams
IEEE 1687	BIST On-demand Using Distributed On-Chip Programmable Data Streams
IEEE1149.1	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
IJTAG	Single-Pin Test Control for Big A, little d Devices Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs Quo Vadis IJTAG.1? Scaling Interactive IJTAG Debug Beyond the Desktop to ATE Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
IJTAG router	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
IJTAG.1	Single-Pin Test Control for Big A, little d Devices Quo Vadis IJTAG.1?
In-Situation Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams
In-System Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams
infant mortality	Automated Die Inking: A Pattern Recognition-based Approach
Information Flow Security	Hardware Trojan Detection Through Information Flow Security Verification
Inking	Automated Die Inking: A Pattern Recognition-based Approach
interconnect test	Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture
Inverse Temperature Dependence	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
IP manufacturability	An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
IR-Drop	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
J
Jitter Analysis	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
jitter decomposition	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
JTAG	Single-Pin Test Control for Big A, little d Devices A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode
L
latent defects	Automated Die Inking: A Pattern Recognition-based Approach
Layout pattern classification	Front-End Layout Reflection for Test Chip Design
layout-aware	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
layout-aware scan diagnosis	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
LBIST	BIST On-demand Using Distributed On-Chip Programmable Data Streams A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode Hierarchical Hybrid EDT-LBIST System
linear regression	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Logic Characterization Vehicle	Front-End Layout Reflection for Test Chip Design
Low power scan	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Low-Dropout Regulator	Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
LSIB	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
M
Manufacturing Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects
marginal faults	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
MBIST	BIST On-demand Using Distributed On-Chip Programmable Data Streams
memory diagnosis	Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
Memory test	A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port modeled in IJTAG
methodology	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Micro-void	Testing TSVs for Micro-void and Pinhole Defects Using OTA
MIMO	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
Mission-Mode Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams
mixed-signal test	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
moving average	Symbol-based Health-Status Analysis in a Core Router System
Multiple chain diagnosis	Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
N
NAND flash	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
Network-on-chip	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
no fault found	Marginal PCB Assembly Defect Detection on DDR3/4 Memory Bus
noise	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
non-coherent sampling	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
non-intrusive test	Nonintrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation
O
on-line testing	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
online testing	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
Outlier analysis	Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Outlier Screens	A VMIN Temperature Shift Outlier Screen for Cold Test Elimination
P
P1687.1	Single-Pin Test Control for Big A, little d Devices
Parallel IJTAG	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
Partial Dynamic Reconfiguration	Self-Test and Self-Repair Method for FPGAs
Pass through a level to reach another	Technique to Test Hierarchical Designs with Multiple Design Levels
path delay faults	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits
Pattern Based Search	Multisite PMIC Fast Trimming with Pattern-based Search Function
pattern recognition	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
PDL	Quo Vadis IJTAG.1?
Performance counters	Run-Time Hardware Trojan Detection Using Performance Counters
physical candidates	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Physical Closure	Interstitial DFT in SpeedCore™
Physical Implementation	Front-End Layout Reflection for Test Chip Design
Physically-Aware	Advancing Test Compression to the Physical Dimension
PMBIST	BIST On-demand Using Distributed On-Chip Programmable Data Streams
PMIC	Multisite PMIC Fast Trimming with Pattern-based Search Function
POST	BIST On-demand Using Distributed On-Chip Programmable Data Streams
Power-On-Self-Test	BIST On-demand Using Distributed On-Chip Programmable Data Streams
Process monitor boxes	Transition Fault Testing for Offline Adaptive Voltage Scaling
productivity gains	Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study
Programmable	BIST On-demand Using Distributed On-Chip Programmable Data Streams
Q
QMR	Self-Test and Self-Repair Method for FPGAs
quality	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
R
Random Jitter (RJ)	A Jitter Separation and BER Estimation Method for Asymmetric Total Jitter Distributions
reduced hits per code INL/DNL test	Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
reliability	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Reliability evaluation	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
resilient system	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
rule discovery	Symbol-based Health-Status Analysis in a Core Router System
run-time	Run-Time Hardware Trojan Detection Using Performance Counters
S
safety analysis	Safety Analysis for Integrated Circuits in the Context of Hybrid Systems
SCAN	Hierarchical Hybrid EDT-LBIST System
Scan architecture	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Scan based test	Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Scan Cell	On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops
scan chain faults	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
scan test	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric Multicycle At-Speed Test Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Scan-based test	On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
security	Thwarting Analog IC Piracy via Combinational Locking Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
self-repair	Self-Test and Self-Repair Method for FPGAs
self-test	Self-Test and Self-Repair Method for FPGAs
Shift-Error	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Shmoo sliver	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
SIB	Increasing IJTAG Bandwidth and Managing Security through Parallel Locking-SIBs
silicon debug	A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
single-wire interface	Single-Pin Test Control for Big A, little d Devices
SJTAG	Quo Vadis IJTAG.1?
skewed-load tests	POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits
small delay defects	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
SMT	Thwarting Analog IC Piracy via Combinational Locking
SOC test	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
SoC yield	An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
soft faults	Self-Test and Self-Repair Method for FPGAs
Software-based self-testing	Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking
specifications testing	A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling
speed-limiting TDF	Exploiting Path Delay Test Generation to Develop Better TDF Tests for Small Delay Defects
SSD	Improvement of the Tolerated Raw Bit-Error Rate in NAND Flash-based SSDs with the Help of Embedded Statistics
static test compaction	POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits
Statistical model	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
statistics	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Subthreshold SoC	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
Switching Activity	Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
symbiotic computing	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
symbiotic system	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
symbolic aggregation approximation	Symbol-based Health-Status Analysis in a Core Router System
System test	A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test
systematic defects	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
systermatic defects	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
T
TEMS Characterization	Taming of the Shmoo
Teradyne	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
Tessent SiliconInsight	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
Test at speed without adding redundant wrapper cells	Technique to Test Hierarchical Designs with Multiple Design Levels
test compaction	Selecting Target Bridging Faults for Uniform Circuit Coverage
Test Compression	Advancing Test Compression to the Physical Dimension
Test Cost	Advancing Test Compression to the Physical Dimension
test cost reduction	Automated Die Inking: A Pattern Recognition-based Approach
Test Coverage	Advancing Test Compression to the Physical Dimension
test data	An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
test generation	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation Selecting Target Bridging Faults for Uniform Circuit Coverage
Test optimisations
Test point insertion	Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Test Program	Use Models for Extending IEEE 1687 to Analog Test
test reordering	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
test scheduling	Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
test set quality	Selecting Target Bridging Faults for Uniform Circuit Coverage
test set reordering	Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
test strategy	Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature
Test time reduction	Modeling Trans-Threshold Correlations for Reducing Functional Test Time in Ultra-Low-Power Systems
testing	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
time interval error	A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links
time series analysis	Symbol-based Health-Status Analysis in a Core Router System
TMR	Self-Test and Self-Repair Method for FPGAs
topographical	Interstitial DFT in SpeedCore™
transients	Self-Test and Self-Repair Method for FPGAs
Transition Delay Test	Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing
transition fault	Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects
Transition fault testing	Transition Fault Testing for Offline Adaptive Voltage Scaling
transition faults	POSTT: Path-oriented Static Test Compaction for Transition Faults in Scan Circuits
TSV test	Testing TSVs for Micro-void and Pinhole Defects Using OTA
Tuning	Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
U
UltraFLEX	Scaling Interactive IJTAG Debug Beyond the Desktop to ATE
uniform random defects	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
USER-SMILE	An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
V
volume diagnosis	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective High-Throughput Multiple Device Diagnosis System
W
wafer geographic	Kernel-based Clustering for Quality Improvement and Excursion Detection
wafer map analysis	The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps
weighted fault coverage	Layout-aware 2-Step Window-based Pattern Reordering for Fast Bridge/Open Test Generation
with more than 2 physical nested hierarchies	Technique to Test Hierarchical Designs with Multiple Design Levels
Y
Yield	Front-End Layout Reflection for Test Chip Design
yield improvement	Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems
Yield Learning	High-Throughput Multiple Device Diagnosis System An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield
yield limiters	Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Yield ramp	DFM-aware Fault Model and ATPG for Intra-Cell and Inter-Cell Defects

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