ITC 2016: INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

1
1149.1	Accessing 1687 Systems Using Arbitrary Protocols
1687	Accessing 1687 Systems Using Arbitrary Protocols
1687.1	Accessing 1687 Systems Using Arbitrary Protocols
3
3D/2.5D Test	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
A
access time minimization	Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
Active learning	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
adaptive test	What We Know After Twelve Years Developing and Deploying Test Data Analytics
Aging Reliability	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Analog	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
analog AC test	SERDES External Loopback Test Using Production Parametric-Test Hardware
Analog ATPG	Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Analog Circuits	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
analog fault coverage	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing
analog fault simulation	Automated Measurement of Defect Tolerance in Mixed-Signal ICs
analog test	Fault Simulation for Analog Test Coverage
Analog-to-Digital Converter	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Analog/RF	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Anomaly Detection	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
ASIC	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
ATE	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools
ATE OS	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
ATE System	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
ATPG	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Automated test Equipment	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
Automatic	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Automatic Test Equipment	Statistical Outlier Screening as a Test Solution Health Monitor
Automatic test pattern generation	Test Point Insertion in Hybrid Test Compression / LBIST Architectures
Automatic test patterns generation	Minimal Area Test Points for Deterministic Patterns
automotive mixed signal	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing
B
Benchmarks	A Suite of IEEE 1687 Benchmark Networks
biclustering	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
biochips	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
board	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
boundary scan	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
bridge fault	Note on Critical-Area-aware Test Pattern Generation and Reordering
built-in self-repair	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Built-in self-test	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Burn In	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
C
C-testability	Logic Characterization Vehicle Design Reflection via Layout Rewiring
cad	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Carbon Nanotube Field Effect Transistor (CNFET)	Defect Tolerance for CNFET-based SRAMs
Cell-aware diagnosis	Diagnosing Cell Internal Defects for FinFET Technology Test Chip Design for Optimal Cell-Aware Diagnosability
Cell-Aware Faults	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Cell-internal faults	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement
Channel Sharing	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Characterization	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Checking	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Compact Footprint	CloudTesting Service In Silicon Diagnostics
compaction	Using Symbolic Canceling to Improve Diagnosis from Compacted Response
Computation Tree Logic	An accurate algorithm for computing mutation coverage in model checking
Concurrent Error Detection	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
concurrent testing	Advanced Test Methodology for Complex SoCs
connectivity test	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Contact Resistance	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Core Network	Uninterrupted Hardware Design
Core Router System	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
Cost-of-Testing	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Cost-of-Yield	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
critical area	Note on Critical-Area-aware Test Pattern Generation and Reordering
cross-layer reliability	Cross-Layer System Reliability Assessment Against Hardware Faults
crosstalk	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
D
Data
Data Mining	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
DDR	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
DDR4	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Debug	1687.1 -- New Connections for a New Standard
defect modeling	Diagnosing Cell Internal Defects for FinFET Technology
defect tolerance	Automated Measurement of Defect Tolerance in Mixed-Signal ICs
Defect-detection	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
defect-oriented test	Automated Measurement of Defect Tolerance in Mixed-Signal ICs Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits
Defect-oriented testing	Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
delay test	Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
delay testing	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Delta-Sigma	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Dependability	Scalable and Reusable Dependability Framework Based on IEEE 1687
dependable computing system	Cross-Layer System Reliability Assessment Against Hardware Faults
design verification	An accurate algorithm for computing mutation coverage in model checking
Design-for-Diagnosis	Test Chip Design for Optimal Cell-Aware Diagnosability
Design-of-Experiments	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
device interface board	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
DFT	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Diagnosis	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis Using Symbolic Canceling to Improve Diagnosis from Compacted Response A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation Logic Characterization Vehicle Design Reflection via Layout Rewiring
Diagnosis with Compressor	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
Diagnostic ATPG	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Diagnostic resolution	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Diagnostics	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Die Level Testing	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Digital microfluidics	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Digital-to-Analog Converter	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Discrete Chirp	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
DPPM	Custom Logic BIST in cutting edge SoC FPGA systems
DRAM	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
DSP-based testing	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
DWA	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Dynamic Bandwidth Management	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns
Dynamic Part Average Testing	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
E
EDT	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Embedded Instruments	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools 1687.1 -- New Connections for a New Standard An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics
extended value algebra	Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
External Loopback	SERDES External Loopback Test Using Production Parametric-Test Hardware
F
Failure Analysis	CloudTesting Service In Silicon Diagnostics
Failure isolation	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Failure Mapping	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
faster-than-at-speed	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Fault Coverage	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Fault Distribution	Defect Tolerance for CNFET-based SRAMs
Fault Injection	Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262
fault modeling	Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Double Pumped Memory Fault Modeling and Test
fault simulation	Fault Simulation for Analog Test Coverage
Fault Tolerance	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
Fault transformation	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement
Fault-detection	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Fault-tolerance	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
Fault-tolerant routing	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Feature Selection	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
FEXT (far-end crosstalk)	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
Filter	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
FinFET technology	Diagnosing Cell Internal Defects for FinFET Technology
FIR filter	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
Fortuitous Detection	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
FPGA	Custom Logic BIST in cutting edge SoC FPGA systems
FPGA Aging	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
Function aware test pattern generation	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
functional test and stress	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
G
GDDR5	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Generation	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Group Delay	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
H
Hardware Design	Uninterrupted Hardware Design
Hardware-in-the-loop simulation	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Hierarchical DFT	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
high speed serial IO	Fault Simulation for Analog Test Coverage
High-Power Testing	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
High-Volume-Manufacturing Testing	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
I
I-Q Balance Test	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
I-Q Signal	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
I2C	Accessing 1687 Systems Using Arbitrary Protocols
IC Stack-up	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
IDDT and Current test	An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics
IEEE 1149.1 JTAG	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools 1687.1 -- New Connections for a New Standard
IEEE 1500 Core Test	1687.1 -- New Connections for a New Standard
IEEE 1500 Core Wrapper	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools
IEEE 1687	Scalable and Reusable Dependability Framework Based on IEEE 1687 A Suite of IEEE 1687 Benchmark Networks
IEEE 1687 IJTAG	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools 1687.1 -- New Connections for a New Standard
IEEE Std. 1687	Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
IEEE Test Standards	1687.1 -- New Connections for a New Standard
IIR filter	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
iJTAG	Scalable and Reusable Dependability Framework Based on IEEE 1687 A Suite of IEEE 1687 Benchmark Networks
Industrial control systems	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
inline inspection	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Intelligent System	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
IR drop	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
ISO 26262	Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262
J
JTAG	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods Accessing 1687 Systems Using Arbitrary Protocols
K
key logic circuit	Does your Locking SIB have a Back Door?
L
Laser Voltage Probing	CloudTesting Service In Silicon Diagnostics
layout analysis	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
LCV	Logic Characterization Vehicle Design Reflection via Layout Rewiring
Location Averaging	What We Know After Twelve Years Developing and Deploying Test Data Analytics
Locking segment insertion bits (LSIBs)	Does your Locking SIB have a Back Door?
Logic BIST	Custom Logic BIST in cutting edge SoC FPGA systems
Logic built-in self-test	Test Point Insertion in Hybrid Test Compression / LBIST Architectures
low pin count test	Advanced Test Methodology for Complex SoCs
low power test	Advanced Test Methodology for Complex SoCs
LUT path delay	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
M
Machine Learning	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Machine-Learning Techniques	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
magnetic coupling	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Matching Score	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
Mean Downtime	An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics
memory	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Memory BIST	Double Pumped Memory Fault Modeling and Test
Memory Repair	Defect Tolerance for CNFET-based SRAMs
Memory Test	Double Pumped Memory Fault Modeling and Test
Memory Test and Repair	A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath
Micro-electrode-dot-array	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Microring resonator	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
MISR	Using Symbolic Canceling to Improve Diagnosis from Compacted Response Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Mixed Signal	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Mixed-Signal	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Mixed-Signal Circuits	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
mixed-signal test	Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Fault Simulation for Analog Test Coverage
model checking	An accurate algorithm for computing mutation coverage in model checking
multi-site testing	Advanced Test Methodology for Complex SoCs Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Multi-Tone	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Multiple fault models	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement
Multiple-core testing	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Multisite	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
N
NEXT (near-end crosstalk)	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
NoC	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
NOC testing	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Noise figure	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Nonlinear Control	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
nonlinear source	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
O
on-chip networks	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
On-chip test controller	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
on-line monitoring	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Online Test	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
open defects	Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits
open-gate defect	Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits
Outliers	Statistical Outlier Screening as a Test Solution Health Monitor
overkills/underkills	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
P
PARSEC	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
part average testing	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing
path delay test	Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
pattern classification	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Pattern Retargeting	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
pattern reuse	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores Advanced Test Methodology for Complex SoCs
Performance	Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process
PFA	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Photonic	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
Placement	Logic Characterization Vehicle Design Reflection via Layout Rewiring
Post-Silicon Validation	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
power analysis attack	Does your Locking SIB have a Back Door?
power delivery network	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
power supply impedance	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Power-Aware BIST synthesis	A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath
probe	Statistical Outlier Screening as a Test Solution Health Monitor
Probe-test flow	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Process Signature	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
process variation prediction	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Process variations	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
Process-aware defenses	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Program	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
property coverage	An accurate algorithm for computing mutation coverage in model checking
R
RAM	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Real Time	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
recycled FPGAs	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
redundancy	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits Uninterrupted Hardware Design
redundancy analysis	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Reliability	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics Custom Logic BIST in cutting edge SoC FPGA systems
reliability modeling	Cross-Layer System Reliability Assessment Against Hardware Faults
Reliability Monitoring	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Resolution	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Resource_Pool	Uninterrupted Hardware Design
retargeting	Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
retention	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Reuse LBIST	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
RF	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
RMA	CloudTesting Service In Silicon Diagnostics
Routing	Logic Characterization Vehicle Design Reflection via Layout Rewiring
S
Scan chain storage	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Scan Design	A Suite of IEEE 1687 Benchmark Networks
scan diagnosis	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Scan Shift	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Scan-based designs	Minimal Area Test Points for Deterministic Patterns
Scan-based testing	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
security	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Self-Calibrating Systems	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
Self-Calibration	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Self-Healing	Uninterrupted Hardware Design
sequential compression	Advanced Test Methodology for Complex SoCs
SERDES	SERDES External Loopback Test Using Production Parametric-Test Hardware
Shadow Flops	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
signal purity	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
signature	Using Symbolic Canceling to Improve Diagnosis from Compacted Response
Silicon characterization	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Silicon Debug	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools
Silicon Diagnosis	CloudTesting Service In Silicon Diagnostics
Silicon TV tuner	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Singulated Die Handling	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
slack-time	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
SoC	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
SoC Test	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns
spatial pattern	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Specification	Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process
spectral testing	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
spin transfer torque magnetic random access memory(STT-MRAM)	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Stability	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Static Random Access Memory (SRAM)	Defect Tolerance for CNFET-based SRAMs
Statistical Analysis Techniques	Statistical Outlier Screening as a Test Solution Health Monitor
statistical post-processing	What We Know After Twelve Years Developing and Deploying Test Data Analytics
symbolic canceling	Using Symbolic Canceling to Improve Diagnosis from Compacted Response
system	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
System Level Test	Accessing 1687 Systems Using Arbitrary Protocols
T
template matching	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Test	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement 1687.1 -- New Connections for a New Standard
Test accuracy	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Test algorithms	Double Pumped Memory Fault Modeling and Test
Test Automation	Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Test chip	Test Chip Design for Optimal Cell-Aware Diagnosability Logic Characterization Vehicle Design Reflection via Layout Rewiring
Test Compaction	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Test compression	Minimal Area Test Points for Deterministic Patterns Test Point Insertion in Hybrid Test Compression / LBIST Architectures An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Test cost	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
test data analytics	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Test generation	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement Note on Critical-Area-aware Test Pattern Generation and Reordering
Test point insertion	Minimal Area Test Points for Deterministic Patterns Test Point Insertion in Hybrid Test Compression / LBIST Architectures
test reordering	Note on Critical-Area-aware Test Pattern Generation and Reordering
Test Standards	An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics
Test Time	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Test-pattern generation	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Testability measures	Test Point Insertion in Hybrid Test Compression / LBIST Architectures
Tester	Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Testing	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Time-Series Analysis	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
timing failure threat	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Timing-Aware BIST synthesis	A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath
Transient faults	Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262
U
unicast-based multicast	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
upper bound computation	Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
V
Validation	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Verification
Voltage Screen	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
volume analysis	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
W
weighted fault coverage	Note on Critical-Area-aware Test Pattern Generation and Reordering
Y
Yield	Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Yield learning	Test Chip Design for Optimal Cell-Aware Diagnosability Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure

Disclaimer | Powered by EasyChair Smart Program