ITC 2016: INTERNATIONAL TEST CONFERENCE

A
Abdelwahid, Mohammed	Diagnosing Cell Internal Defects for FinFET Technology
Abdollahian, Ayub	Advanced Test Methodology for Complex SoCs
Abraham, Jacob A.	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
Adham, Saman	Double Pumped Memory Fault Modeling and Test TBABIST Design for Characterization and Testing of Embedded STT-MRAM
Aflaki, Aman	SERDES External Loopback Test Using Production Parametric-Test Hardware
Ahmadi, Ali	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Ahmed, Sheikhmukhtar	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Aitken, Rob	Anticipated Test Challenges of Emerging Devices
Alam, Md Mahbub	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
Alhelaly, Soha	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Alt, Juergen	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
Amyeen, M. Enamul	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation The Journey to root cause - Part I
Arai, Masayuki	Note on Critical-Area-aware Test Pattern Generation and Reordering
Armstrong, Dave	Moore’s Law is Done and Heterogeneous Integration is Taking Off Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Arora, Shalini	SERDES External Loopback Test Using Production Parametric-Test Hardware
Asada, Kunihiro	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Asami, Koji	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
B
Banerjee, Suvadeep	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
Bawaskar, Neerja	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Bernardi, Paolo	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Bhaskaran, Bonita	Advanced Test Methodology for Complex SoCs
Bhattacharya, Parthajit	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
Biswas, Prasenjit	Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
Biswas, Prasenjit	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
Biswas, Sounil	SERDES External Loopback Test Using Production Parametric-Test Hardware
Blanton, R. D.	Logic Characterization Vehicle Design Reflection via Layout Rewiring Test Chip Design for Optimal Cell-Aware Diagnosability
Blanton, Ronald	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Bosio, Alberto	Cross-Layer System Reliability Assessment Against Hardware Faults Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Bourland, Mike	Advanced Node Product and Technology Enablement Vehicles
Bulaga, Ray	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Butler, Kenneth	Statistical Outlier Screening as a Test Solution Health Monitor What We Know After Twelve Years Developing and Deploying Test Data Analytics
C
Cairl, Brian	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Canal, Ramon	Cross-Layer System Reliability Assessment Against Hardware Faults
Cantoro, Riccardo	A Suite of IEEE 1687 Benchmark Networks
Carulli, John	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Chadalavada, Sailendra	Advanced Test Methodology for Complex SoCs
Chakrabarty, Krishnendu	Defect Tolerance for CNFET-based SRAMs Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Chakrabarty, Krishnendu	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Chandrasekar, Maheshwar	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Chao, Huina	An accurate algorithm for computing mutation coverage in model checking
Chatterjee, Abhijit	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Chatterjee, Abhijit	Efficient Cross-Layer Concurrent Error Detection In Non-Linear Control Systems Using Mapped Predictive Check States
Chatzidimitriou, Athanasios	Cross-Layer System Reliability Assessment Against Hardware Faults
Chaudhary, Nitin	Fault Simulation for Analog Test Coverage
Chen, Degang	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Chen, Jifeng	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Chen, Yong-Xiao	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Chen, Zaiman	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Cheng, Kwang-Ting	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Cheng, Wu-Tung	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Chintaluri, Ashwin	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Chittora, Atul	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Chou, Yung-Fa	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Contreras, Gustavo	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Coyette, Anthony	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Crafts, James	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Cron, Adam	Custom Logic BIST in cutting edge SoC FPGA systems
Crouch, Al	Does your Locking SIB have a Back Door?
Crouch, Alfred	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools 1687.1 -- New Connections for a New Standard
D
Daasch, Robert	What We Know After Twelve Years Developing and Deploying Test Data Analytics
Dang, Dharanidhar	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
Datla Jagannadha, Pavan Kumar	Advanced Test Methodology for Complex SoCs
De Man, Willy	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing
Deforge, John	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Desineni, Rao	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Devadze, Sergei	A Suite of IEEE 1687 Benchmark Networks
Devanathan, V.R.	A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath
Deyati, Sabyasachi	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Di Carlo, Stefano	Cross-Layer System Reliability Assessment Against Hardware Faults
Di Natale, Giorgio	Cross-Layer System Reliability Assessment Against Hardware Faults
Di Natale, Giorgio	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Do, Vu	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Dobbelaere, Wim	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Dworak, Jennifer	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Dworak, Jennifer	Does your Locking SIB have a Back Door?
E
Eklow, Bill	Test and Supply Chain Challenges for Heterogeneous Integration
Engels, Daniel	Does your Locking SIB have a Back Door?
Esen, Baris	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
F
Fan, Jenny	CloudTesting Service In Silicon Diagnostics
Fan, Yongquan	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Fernandes, Sherwin	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Fisette, Rick	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Forte, Domenic	Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
Fujiwara, Hideo	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Fynan, Phillip	Logic Characterization Vehicle Design Reflection via Layout Rewiring
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Garcia, Allison	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Ghani Zadegan, Farrokh	A Suite of IEEE 1687 Benchmark Networks Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
Gielen, Georges	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits
Gielen, Georges	Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Gizopoulos, Dimitris	Cross-Layer System Reliability Assessment Against Hardware Faults
Goel, Neha	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Gonzalez, Antonio	Cross-Layer System Reliability Assessment Against Hardware Faults
Goteti, Prashant	Fault Simulation for Analog Test Coverage
Gu, Xinli	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
Guerriero, Andrea	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Gupta, Saurabh	Does your Locking SIB have a Back Door?
H
Han, Dong Kwan	Diagnosing Cell Internal Defects for FinFET Technology
Ho, Tsung-Yi	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Hoops, Dirk	Statistical Outlier Screening as a Test Solution Health Monitor
Hou, Chih-Sheng	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Hsu, Chun-Kai	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Hsu, Yu-Tang	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
Huang, Kenneth	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Huang, Shi-Yu	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Huang, Yu	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Hwong, Daphne	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
I
Ibrahim, Ahmed	An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics Scalable and Reusable Dependability Framework Based on IEEE 1687
Ibrahim, Mohamed	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Iizuka, Tetsuya	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Ikeno, Rimon	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Inuyama, Shingo	Note on Critical-Area-aware Test Pattern Generation and Reordering
Ishida, Masahiro	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Iwasaki, Kazuhiko	Note on Critical-Area-aware Test Pattern Generation and Reordering
J
Jain, Anurag	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Janney, John	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Jiang, Li	Defect Tolerance for CNFET-based SRAMs
Jin, Shi	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
Johnson, Jim	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools 1687.1 -- New Connections for a New Standard
Johnson, Mark	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Johnson, Michael	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Joseph, Arun	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Jutman, Artur	A Suite of IEEE 1687 Benchmark Networks
K
Kadam, Gurunath	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
Kale, Sumant	A Reconfigurable Built-in Memory Self-repair Architecture for Heterogeneous Cores with Embedded BIST Datapath
Kaliorakis, Manolis	Cross-Layer System Reliability Assessment Against Hardware Faults
Kancharla, Sravana	Does your Locking SIB have a Back Door?
Kang, Seung H.	Tailoring Design and Test Methodologies to Validate STT-MRAM as High-Performance Nonvolatile RAM
Kapur, Rohit	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
Karri, Ramesh	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Kayse, Jordan	Does your Locking SIB have a Back Door?
Keim, Martin	1687.1 -- New Connections for a New Standard
Keliris, Anastasis	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Kerkhoff, Hans	An IJTAG-Compatible IDDT Embedded Instrument for Health Monitoring and Prognostics Scalable and Reusable Dependability Framework Based on IEEE 1687
Khatibzadeh, Amir	Hardware Security Assurance: Challenges and Opportunities
Khorrami, Farshad	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Kim, Dongok	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Kobayashi, Haruo	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Kobayashi, Osamu	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Kochte, Michael	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Kojima, Junya	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Konda, Baalaji	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Kong, Luning	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Kooli, Maha	Cross-Layer System Reliability Assessment Against Hardware Faults
Krenz-Baath, Rene	Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
Krishnamurthy, Prashanth	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Kulkarni, Prashant	The DFT Challenges and Solutions for the ARM Mali-Mimir GPU
Kumar, Sandeep	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Kumar, Santosh	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Kundu, Subhadip	Handling Wrong Mapping: A New Direction towards Better Diagnosis with Low Pin Convolution Compressors
Kusaka, Takashi	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Kwai, Ding-Ming	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
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Lai, Amy	Double Pumped Memory Fault Modeling and Test
Lai, Kelvin Yi-Tse	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Lakshmanan, Manu	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Larsson, Erik	A Suite of IEEE 1687 Benchmark Networks Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks
Lee, Chen-Yi	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Lee, Kuen-Jong	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains Output Bit Selection Methodology for Test Response Compaction
Leisenberger, Friedrich	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Ley, Adam W	Testing for Connectivity to DDR Memory at Board- and System-level: Challenges, Guidance and Success for Boundary-Scan-based Methods
Li, Hua	Uninterrupted Hardware Design
Li, Huawei	An accurate algorithm for computing mutation coverage in model checking
Li, Jin-Fu	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Li, Tianjian	Defect Tolerance for CNFET-based SRAMs
Li, Tim	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns
Li, Xiaowei	An accurate algorithm for computing mutation coverage in model checking
Li, Xin	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Li, Zipeng	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Liang, Xiaoyao	Defect Tolerance for CNFET-based SRAMs
Liao, H.J.	Double Pumped Memory Fault Modeling and Test
Lien, Wei-Cheng	Output Bit Selection Methodology for Test Response Compaction
Lim, Carlston	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Lin, Xijiang	Scan-Based Low Power Test Generation
Liu, Bo	An accurate algorithm for computing mutation coverage in model checking
Liu, Yingdi	Minimal Area Test Points for Deterministic Patterns
Liu, Zeye	Logic Characterization Vehicle Design Reflection via Layout Rewiring Test Chip Design for Optimal Cell-Aware Diagnosability
Lo, Chih-Yen	A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Loranger, Marc	Probe Challenges are Changing Rapidly
Lu, Binghua	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Lu, Shyue-Kung	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
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Magdaleno, Nelson	Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process
Magstadt, Benjamin	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Mahapatra, Rabi	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability
Maier, Gary	Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Makris, Yiorgos	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Maldonado, Andres	The Journey to root cause - Part II
Maniatakos, Michail	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Manya, Cynthia	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Mark, Dave	CloudTesting Service In Silicon Diagnostics
Matthijs, Koen	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing
Maxwell, Peter	Four Challenging Insights about Fault Coverage
McAleenan, Roger	Millimeter Systems for Production
Mclaurin, Teresa	DFT Test Considerations for Low Power Devices The DFT Challenges and Solutions for the ARM Mali-Mimir GPU
Mehta, Shrenik	Overview of the Automotive Functional Safety Standard ISO 26262 - Part II Tools and Methods
Meng, Fanjin	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Miglierina, Riccardo	Automated Measurement of Defect Tolerance in Mixed-Signal ICs
Miki, Takahiro	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Mittal, Soumya	Logic Characterization Vehicle Design Reflection via Layout Rewiring Test Chip Design for Optimal Cell-Aware Diagnosability
Moghaddam, Elham	Test Point Insertion in Hybrid Test Compression / LBIST Architectures Minimal Area Test Points for Deterministic Patterns
Mohammed, Mobashir	Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process
Mohyar, Shaiful Nizam Bin	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
Montazeri, Mehrdad	A Suite of IEEE 1687 Benchmark Networks
Mukherjee, Nilanjan	Test Point Insertion in Hybrid Test Compression / LBIST Architectures Minimal Area Test Points for Deterministic Patterns
Muldrey, Barry	DE-LOC: Design Validation and Debugging with Limited Observation and Control, Pre- and Post-Silicon, for Mixed-Signal Systems
Murakami, Masahiro	I-Q Signal Generation Techniques for Communication IC Testing and ATE Systems
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Naeimi, Helia	STTRAM Overview -- Circuit and Architecture Perspective
Nahar, Amit	Statistical Outlier Screening as a Test Solution Health Monitor Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow What We Know After Twelve Years Developing and Deploying Test Data Analytics
Nakamura, Takayuki	Novel Crosstalk Evaluation Method for High-Density Signal Traces Using Clock Waveform Conversion Technique
Nakura, Toru	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Natarajan, Suriyaprakash	Fault Simulation for Analog Test Coverage
Ng, Wai Tung	Transient Testing of Integrated Power Output Stages
Niewenhuis, Benjamin	Logic Characterization Vehicle Design Reflection via Layout Rewiring Test Chip Design for Optimal Cell-Aware Diagnosability
Noble, Brian	Active Reliability Monitor: Defect Level Extrinsic Reliability Monitoring
Noman, Mohammed	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
O
O'Connell, Cormac	Double Pumped Memory Fault Modeling and Test
Orr, Bob	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
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Pan, Yan	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Papavramidou, Panagiota	Memory Repair for High Fault Rates
Parimi, Nitin	P1687.1 – Beyond the TAP
Park, Stephen	Diagnosing Cell Internal Defects for FinFET Technology
Pas, Michael	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Politano, Gianfranco Michele Maria	Cross-Layer System Reliability Assessment Against Hardware Faults
Portolan, Michele	Accessing 1687 Systems Using Arbitrary Protocols
Poulson, Neils	Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools
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Qin, Xiaopeng	Uninterrupted Hardware Design
R
Rajanarayanan, Raghuraman	Custom Logic BIST in cutting edge SoC FPGA systems
Rajski, Janusz	Test Point Insertion in Hybrid Test Compression / LBIST Architectures Minimal Area Test Points for Deterministic Patterns
Raychowdhury, Arijit	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Rearick, Jeff	IEEE P1687.1: Opening New Portals to IJTAG Networks Four Challenging Insights about Fault Coverage
Reddy, Sudhakar	Minimal Area Test Points for Deterministic Patterns
Riera Villanueva, Marc	Cross-Layer System Reliability Assessment Against Hardware Faults
Roberts, Gordon	Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms
Rose, Larry	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Rudack, Markus	Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing
S
Sadi, Mehdi	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Saleem, Kamran	Using Symbolic Canceling to Improve Diagnosis from Compacted Response
Salehghaffari, Hossein	Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems
Sarangi, Shantanu	Advanced Test Methodology for Complex SoCs
Sarson, Peter	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Savino, Alessandro	Cross-Layer System Reliability Assessment Against Hardware Faults
Schat, Jan	Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262
Schatzberger, Gregor	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Sekar, Kannan	Pylon: Towards an Integrated Customizable Volume Diagnosis Infrastructure
Sequeira, Jyotsna	Fault Simulation for Analog Test Coverage
Sharma, Ramesh	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Shaw, David	Statistical Outlier Screening as a Test Solution Health Monitor
Shelley, John	Challenges with high volume mmWave test cells
Shi, Jintao	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Shimanouchi, Masashi	SERDES External Loopback Test Using Production Parametric-Test Hardware
Shofner, Geoff	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Siddhartha, Siddhartha	Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages
Sivaram, At	CloudTesting Service In Silicon Diagnostics
Smith, Tony	Package Interconnect Options for mmWave Applications
Sonawane, Milind	Advanced Test Methodology for Complex SoCs
Sonza Reorda, Matteo	A Suite of IEEE 1687 Benchmark Networks
Sprague, Douglas	ASICS End-To-End Automated Test Program Generation & Diagnostics Enablement
Strojwas, Marcin	Logic Characterization Vehicle Design Reflection via Layout Rewiring
Su, Yu	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
Sudani, Siva	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
Sun, Yi	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Sunter, Stephen	Automated Measurement of Defect Tolerance in Mixed-Signal ICs
Swarup, Bhunia	The Enemies of IC Security and Trust and How to Test Them
T
Tang, Huaxing	Diagnosing Cell Internal Defects for FinFET Technology
Tang, Jack	Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Tang, Pin-Hao	An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains
Tatman, David	Overview of the Automotive Functional Safety Standard ISO 26262 - Part I Design Impact
Tehranipoor, Mark	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization
Terao, Naoki	Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Touba, Nur	Using Symbolic Canceling to Improve Diagnosis from Compacted Response
Tran, Dat	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning
Tsai, Hans	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Tsao, Cheng-Hung	A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
Tselonis, Sotiris	Cross-Layer System Reliability Assessment Against Hardware Faults
Tsertov, Anton	A Suite of IEEE 1687 Benchmark Networks
Tyszer, Jerzy	Test Point Insertion in Hybrid Test Compression / LBIST Architectures Minimal Area Test Points for Deterministic Patterns
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Udyavar, Jaidev	Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
Unnithan, Akhilesh	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration
V
Valerio, Alessandro	Automated Measurement of Defect Tolerance in Mixed-Signal ICs
Vallero, Alessandro	Cross-Layer System Reliability Assessment Against Hardware Faults
Vanhooren, Ronny	Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits Automatic Test Signal Generation for Mixed-Signal Integrated Circuits Using Circuit Partitioning and Interval Analysis
Varma, Namit	Custom Logic BIST in cutting edge SoC FPGA systems
Vassilev, Apostol	Is Automated Testing the Panacea Cryptography Needs to Deliver Promised Security Assurances?
Venini, Federico	Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
Venkataraman, Srikanth	A Novel Diagnostic Test Generation Methodology and Its Application in Production Failure Isolation
Verma, Anant	RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners
von Staudt, Hans Martin	Got the Power? Test and DfT of Mobile Power Management ICs (PMICs)
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Waayers, Tom	Extending the application of IEEE 1687
Walker, Duncan	Fault Tolerant Photonic Router for Network-on-Chip with High Reliability Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
Wang, Li-C
Wang, Ran	Testing of Interposer-Based 2.5D Integrated Circuits
Wang, Tiancheng	An accurate algorithm for computing mutation coverage in model checking
Wang, Ting-Chi	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Wang, Zhiyuan	Uninterrupted Hardware Design
Winemberg, Leroy	BIST-RM: BIST-assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Wu, Cheng-Hung	Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement
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Xanthopoulos, Constantinos	Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow
Xiang, Dong	A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Xu, Liuming	Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns
Xu, Qiang	Defect Tolerance for CNFET-based SRAMs
Xue, Yang	Diagnostic Resolution Improvement with Active Learning Guided Physical Failure Analysis
Y
Yang, Wu	Diagnosing Cell Internal Defects for FinFET Technology
Yasuji, Oyama	CloudTesting Service In Silicon Diagnostics
Yilmaz, Mahmut	Advanced Test Methodology for Complex SoCs
Yoon, Insik	EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
Yu, Jiunn-Der	Double Pumped Memory Fault Modeling and Test
Yu, Po-Hsien	Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Z
Zawada, Justyna	Test Point Insertion in Hybrid Test Compression / LBIST Architectures
Zhang, Benhai	CloudTesting Service In Silicon Diagnostics
Zhang, Fanchen	Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-Aware Fault Detection with Scan Shift Capture
Zhang, Peilai	Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
Zhang, Zhaobo	Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System
Zhang, Zhigao	Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-Limited, Large SoC Challenges
Zheng, Chih-Chieh	Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects
Zhuang, Yuming	Low Cost Ultra-Pure Sine Wave Generation with Self Calibration

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