EWDTS 2026: 2026 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM

This page contains an index consisting of author-provided keywords.

3
3D integrated circuits	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
3D V-NAND	Architectural Innovations and Engineering Strategies in 3D V-NAND Flash Memory: From Planar Scaling Limitations to Advanced Integration
3D-IC	TSV Assignment in 3DIC Based on SAT Solvers
A
absolute encoders	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
Accelerator	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
Accelerator architectures	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
access control list	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
Active Matrix OLED	Driving Innovation in Organic Light-Emitting Diode Technology: A Case Study of Strategic Approaches in Advancing OLED Systems
Adaptive Antenna Array (AAA)	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
adaptive stress redistribution	Adaptive Stress Redistribution For Improving The Long-Term Reliability Of Analog CMOS Integrated Circuits
AES	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
aging performace monitor	Operating-Point-Aware Aging Performance Monitoring And Adaptive Compensation For Analog Integrated Circuits
AI agents	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
AI-Driven Production Optimization	Driving Innovation in Organic Light-Emitting Diode Technology: A Case Study of Strategic Approaches in Advancing OLED Systems
Analog Circuit	PAC-GAT: Physics-Aware Graph Transfer Learning for Data-Efficient Cross-Technology Analog Performance Prediction
analog CMOS	Adaptive Stress Redistribution For Improving The Long-Term Reliability Of Analog CMOS Integrated Circuits
arbitration	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
ASIC bring-up	Lifecycle of an Educational CPU: From RTL to Silicon Validation
authorization	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
availability	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
B
bandgap narrowing	Physical Modeling and TCAD Simulation of p-GaN Gate HEMT Structures for Microwave Applications
benchmark methodology	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks
bounded model checking	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks
Breakdown voltage	Physics Based TCAD Extraction of Breakdown Voltage Limiting Factors in p-GaN Gate HEMTs
breast cancer	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
C
capability tokens	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
Caravel	Lifecycle of an Educational CPU: From RTL to Silicon Validation
CatBoost	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery
circuit simulation	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
circular array	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
classification-guided module	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
clinical decision support	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
clinical information extraction	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
Clock Gating	Hierarchical Power Exploration and Optimization of A RISC-V Processor
CMOS	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
CMOS-under-array	Architectural Innovations and Engineering Strategies in 3D V-NAND Flash Memory: From Planar Scaling Limitations to Advanced Integration
code compression	Shrinking RISC-V Cores Through Huffman Re-Encoding of Instructions
Computer Vision	Path-planning simulation for logistic robotic workspaces
congestion prediction	Routing Optimization with the Use of Modern Machine Learning Algorithms
consistency checking	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
convolutional neural network	Routing Optimization with the Use of Modern Machine Learning Algorithms
CORDIC	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
Cross-Layer Optimization	Hierarchical Power Exploration and Optimization of A RISC-V Processor
Cross-Technology Migration	PAC-GAT: Physics-Aware Graph Transfer Learning for Data-Efficient Cross-Technology Analog Performance Prediction
custom function unit	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
custom instructions	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
cylindrical array	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
cytoreduction	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
D
D2D interconnects	Comprehensive Analysis of Fault Modeling and Test Strategies for Advanced Die-to-Die Interconnects
data quality	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
decoder	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
deep learning	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
deep supervision	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
defect injection	Accelerated Memory Fault Modeling and Test Algorithm Generation through Automated Inductive Analysis
defects	Comprehensive Analysis of Fault Modeling and Test Strategies for Advanced Die-to-Die Interconnects
delegation	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
Digital Signal Processing (DSP)	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
distributed magnetomotive force	Parametric Analysis of Nonuniform Winding Distribution in a Lifting Electromagnet
DMA	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
DPA	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
drift-diffusion transport	Physical Modeling and TCAD Simulation of p-GaN Gate HEMT Structures for Microwave Applications
E
ego-motion cancellation	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
electromagnet	Parametric Analysis of Nonuniform Winding Distribution in a Lifting Electromagnet
electromagnetic device design	Machine Learning-Assisted Design of Electromagnetic Systems
embedded systems	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
Endometrial cancer	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery
ESP32	A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
F
fan-out	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
fault injection	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
fault model	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
fault modeling	Comprehensive Analysis of Fault Modeling and Test Strategies for Advanced Die-to-Die Interconnects Accelerated Memory Fault Modeling and Test Algorithm Generation through Automated Inductive Analysis
feature pyramid	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
feature-level fusion	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
firewall policy anomaly	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
Flash memory architecture	Architectural Innovations and Engineering Strategies in 3D V-NAND Flash Memory: From Planar Scaling Limitations to Advanced Integration
Flexible Displays	Driving Innovation in Organic Light-Emitting Diode Technology: A Case Study of Strategic Approaches in Advancing OLED Systems
Floating-Point Arithmetic	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
floating-point unit sharing	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
formal equivalence checking	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks
formal verification	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
FPGA	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
Free RTOS	A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
full-scale skip connections	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
G
Gallium Nitride	Physics Based TCAD Extraction of Breakdown Voltage Limiting Factors in p-GaN Gate HEMTs
GAP	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
general matrix multiplication (GEMM)	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
geometric query	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
Global Navigation Satellite Systems (GNSS)	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
Graph Attention Networks	PAC-GAT: Physics-Aware Graph Transfer Learning for Data-Efficient Cross-Technology Analog Performance Prediction
graph partitioning	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
GraphSAGE	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
H
Hardware	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
hardware security	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
hardware-software codesign	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
hardware/software codesign	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
Helmholtz equation	Iterative Algorithm for a Nonlocal Contact Problem for the Modified Helmholtz Equation
hierarchical restructuring	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
High Electron Mobility Transistors	Physics Based TCAD Extraction of Breakdown Voltage Limiting Factors in p-GaN Gate HEMTs
Huffman coding	Shrinking RISC-V Cores Through Huffman Re-Encoding of Instructions
hybrid loss	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
I
image segmentation	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
instruction ROM	Shrinking RISC-V Cores Through Huffman Re-Encoding of Instructions
INT8 inference	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
interconnect testing	Comprehensive Analysis of Fault Modeling and Test Strategies for Advanced Die-to-Die Interconnects
Internet of Things	A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
interval tree	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
inverter	Role of Power Supply Voltage in Laser-Induced SEL in a 130 nm PLL Circuit
IoT security	A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
iterative algorithm	Iterative Algorithm for a Nonlocal Contact Problem for the Modified Helmholtz Equation
K
Kalman filter	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
L
large language models	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
laser	Role of Power Supply Voltage in Laser-Induced SEL in a 130 nm PLL Circuit
layout connectivity tracing	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
LightGBM	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery
Low-Power Design	Hierarchical Power Exploration and Optimization of A RISC-V Processor
low-resource languages	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
M
machine learning	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer Machine Learning-Assisted Design of Electromagnetic Systems Routing Optimization with the Use of Modern Machine Learning Algorithms Cross-Technology RTL Timing Prediction Using Multilayer Neural Network
Machine Learning (ML)	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
Machine-learning	Path-planning simulation for logistic robotic workspaces
magnetic equivalent circuit	Parametric Analysis of Nonuniform Winding Distribution in a Lifting Electromagnet
mammography	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
Manufacturing Innovation	Driving Innovation in Organic Light-Emitting Diode Technology: A Case Study of Strategic Approaches in Advancing OLED Systems
Mathcad	Iterative Algorithm for a Nonlocal Contact Problem for the Modified Helmholtz Equation
maximum operating frequency	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
MaxSAT	TSV Assignment in 3DIC Based on SAT Solvers
memory testing	Accelerated Memory Fault Modeling and Test Algorithm Generation through Automated Inductive Analysis
METIS	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
microcontroller	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
ML accelerator	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
MS-SSIM	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
Multi-stack integration	Architectural Innovations and Engineering Strategies in 3D V-NAND Flash Memory: From Planar Scaling Limitations to Advanced Integration
multicore ASIC	Lifecycle of an Educational CPU: From RTL to Silicon Validation
multilayer routing	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
multimodal detection	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
mutation testing	How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
N
negotiated congestion	Routing Optimization with the Use of Modern Machine Learning Algorithms
network security	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
NFC	A Standalone ESP32-Based NFC Terminal for Platform-Independent Integration: Hardware Architecture, Non-Blocking Firmware, and Field Deployment
nonlocal contact problem	Iterative Algorithm for a Nonlocal Contact Problem for the Modified Helmholtz Equation
nonuniform winding distribution	Parametric Analysis of Nonuniform Winding Distribution in a Lifting Electromagnet
O
OAuth 2.0	Comparative Evaluation of Offline and Online Authorization for AI Agents under Authorization-Server Failure
Object Recognition	Path-planning simulation for logistic robotic workspaces
obstacle avoidance	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
OLED Display Technology	Driving Innovation in Organic Light-Emitting Diode Technology: A Case Study of Strategic Approaches in Advancing OLED Systems
on/off state	THE LEAKAGE MINIMIZATION METHOD FOR THE TRANSMISSION GATE DESIGN WITH THIN OXIDE TRANSISTORS
oncology	Parser Faults and Document Faults: Extracting Oncology Data from Armenian Template-Based Discharge Summaries with Rules and a Local LLM
operability classification	Machine Learning-Assisted Design of Electromagnetic Systems
Operand Isolation	Hierarchical Power Exploration and Optimization of A RISC-V Processor
operating-point	Operating-Point-Aware Aging Performance Monitoring And Adaptive Compensation For Analog Integrated Circuits
operational transconductance amplifier	Adaptive Stress Redistribution For Improving The Long-Term Reliability Of Analog CMOS Integrated Circuits
ovarian cancer	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
P
p-bits PSL	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
p-GaN gate	Physics Based TCAD Extraction of Breakdown Voltage Limiting Factors in p-GaN Gate HEMTs
pan-tilt-zoom	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
parallel computing	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
parameter prediction	Machine Learning-Assisted Design of Electromagnetic Systems
Performance Prediction	PAC-GAT: Physics-Aware Graph Transfer Learning for Data-Efficient Cross-Technology Analog Performance Prediction
personalized medicine	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
phase-locked loop (PLL)	Role of Power Supply Voltage in Laser-Induced SEL in a 130 nm PLL Circuit
physical design	TSV Assignment in 3DIC Based on SAT Solvers Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
physical design automation	Routing Optimization with the Use of Modern Machine Learning Algorithms
Physics-Aware Transfer Learning	PAC-GAT: Physics-Aware Graph Transfer Learning for Data-Efficient Cross-Technology Analog Performance Prediction
PID control	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
place and route	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
polarization models	Physical Modeling and TCAD Simulation of p-GaN Gate HEMT Structures for Microwave Applications
post-silicon validation	Lifecycle of an Educational CPU: From RTL to Silicon Validation
power supply voltage	Role of Power Supply Voltage in Laser-Induced SEL in a 130 nm PLL Circuit
predecoding	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
processor test	Lifecycle of an Educational CPU: From RTL to Silicon Validation
pull-up/pull-down transistors	THE LEAKAGE MINIMIZATION METHOD FOR THE TRANSMISSION GATE DESIGN WITH THIN OXIDE TRANSISTORS
Q
quadtree	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
R
R*-tree	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
Random Forest	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery
receiver	Operating-Point-Aware Aging Performance Monitoring And Adaptive Compensation For Analog Integrated Circuits
rectilinear spanning graph	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
Recursive Least Squares (RLS)	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
redundancy	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
reinforcement learning	Routing Optimization with the Use of Modern Machine Learning Algorithms
reliability	Comprehensive Analysis of Fault Modeling and Test Strategies for Advanced Die-to-Die Interconnects Adaptive Stress Redistribution For Improving The Long-Term Reliability Of Analog CMOS Integrated Circuits
resectability prediction	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
RGB-IR fusion	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
RISC-V	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator Shrinking RISC-V Cores Through Huffman Re-Encoding of Instructions A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization Hierarchical Power Exploration and Optimization of A RISC-V Processor A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
Robotics	Path-planning simulation for logistic robotic workspaces
routing algorithms	TSV Assignment in 3DIC Based on SAT Solvers
routing optimization	Routing Optimization with the Use of Modern Machine Learning Algorithms
RTL timing prediction	Cross-Technology RTL Timing Prediction Using Multilayer Neural Network
RTLLM	How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
RVC	Shrinking RISC-V Cores Through Huffman Re-Encoding of Instructions
S
S-box	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
SAT solver	TSV Assignment in 3DIC Based on SAT Solvers
SCA	Probabilistic Spin-Logic Implementations of AES S-Boxes: Enhancing Security Against Differential Power Analysis
self-compensation	Operating-Point-Aware Aging Performance Monitoring And Adaptive Compensation For Analog Integrated Circuits
sensor fusion	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
shadowing	Automated Detection of Logical Anomalies in Network Access Control Lists: A Set-Theoretic Approach
shared FPU	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
Side Lobe Canceller (SLC)	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
single-event latch-up (SEL)	Role of Power Supply Voltage in Laser-Induced SEL in a 130 nm PLL Circuit
source-drain leakage current	THE LEAKAGE MINIMIZATION METHOD FOR THE TRANSMISSION GATE DESIGN WITH THIN OXIDE TRANSISTORS
spatial index	Spatial Index Performance Comparison for Connectivity Tracing in Static VLSI Layouts
Spatial Unrolling	Run-time Configurable CORDIC Accelerator for DSP and ML Applications
SPICE simulation	Accelerated Memory Fault Modeling and Test Algorithm Generation through Automated Inductive Analysis
Square Root Free QR Decomposition (SRF QRD)	Circular/Cylindrical Adaptive Arrays for Navigation Signal Receivers
standart-cell libraries	Cross-Technology RTL Timing Prediction Using Multilayer Neural Network
static timing analysis	Hierarchical Restructuring of Flat Decoder Architectures: Design and Performance Analysis
Steiner tree construction	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
Substrate	Physics Based TCAD Extraction of Breakdown Voltage Limiting Factors in p-GaN Gate HEMTs
Support Vector Machine	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery
system-on-chip (SoC)	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
T
task scheduling	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator
temporal induction	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks
test algorithm	Accelerated Memory Fault Modeling and Test Algorithm Generation through Automated Inductive Analysis
testbench quality	How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
thin oxide transistor	THE LEAKAGE MINIMIZATION METHOD FOR THE TRANSMISSION GATE DESIGN WITH THIN OXIDE TRANSISTORS
through-silicon vias	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
timing estimation	Cross-Technology RTL Timing Prediction Using Multilayer Neural Network
TinyML	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
transistor aging	Adaptive Stress Redistribution For Improving The Long-Term Reliability Of Analog CMOS Integrated Circuits
TSV assignment	TSV Assignment in 3DIC Based on SAT Solvers
tumor microenvironment	A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
tunneling effects	Physical Modeling and TCAD Simulation of p-GaN Gate HEMT Structures for Microwave Applications
U
U-Net	A Lightweight Full-Scale Skip-Connected U-Net with Classification Guidance and a Hybrid Loss for Tumor Region Segmentation in Mammography Images
UAV detection	Evaluation of Feature Pyramid Fusion Levels for RGB-IR UAV Detection
unsupervised learning	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
V
Verilog benchmarks	How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
Verilog generation	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks
VerilogEval	How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
Vertical scaling	Architectural Innovations and Engineering Strategies in 3D V-NAND Flash Memory: From Planar Scaling Limitations to Advanced Integration
VerySimpleCPU	Lifecycle of an Educational CPU: From RTL to Silicon Validation
VexRiscv	A Hardware-Accelerated Quantized CNN Architecture for MNIST Classification Using RISC-V Customization
visual servoing	Real-Time Electro-Optical Object Tracking on NVIDIA Jetson Orin NX: A World-Angle Estimation Architecture for Encoder-Instrumented Pan–Tilt–Zoom Platforms
VLSI routing	Efficient Multi-Die 3D IC Routing Tool with Spanning-Graph-Based Obstacle-Avoiding Steiner Tree Construction
voltage drop	THE LEAKAGE MINIMIZATION METHOD FOR THE TRANSMISSION GATE DESIGN WITH THIN OXIDE TRANSISTORS
W
weighted edge cut	Machine Learning-Based Multi-Objective Graph Partitioning for Distributed Simulation of Large-Scale Circuits
X
X-HEEP	RFCA: Reusing Fused Multiply-Add between the CPU and the Accelerator
XGBoost	A Multimodal Machine Learning Framework for Personalized Perioperative Risk Prediction in Endometrial Cancer Surgery A Multiparametric Machine-Learning Framework for Predicting Complete Cytoreduction and Personalizing Treatment Selection in Advanced Epithelial Ovarian Cancer
Y
Yosys	Open-Source Formal Equivalence as an Oracle for LLM-Generated RTL – Verdict Anatomy over 8,000 Checks How Strong Are the Reference Testbenches of VerilogEval v2 and RTLLM v2.0? A Mutation-Based Audit
Z
zero-injection logic	A Hardware Scheduler and Task Dispatcher Forming a Hybrid ML Accelerator

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