ABSTRACT. This work reports the ASIC implementation and initial board-level bring-up of VSCPU3x, a system comprising three educational VerySimpleCPU cores. The design is based on previous Mastermind work, mimicking a subset of its functionality with three VSCPU cores named Code Maker, Control Tower, and Agent 0. The three cores are complemented by 24~KiB of local SRAM macros, a small shared memory with memory-mapped GPIO, and a UART. The RTL-to-GDSII flow was carried out with OpenLane, and the design was fabricated through the ChipIgnite 2206Q shuttle within the Caravel harness SoC. Timing issues identified after tape-out are discussed, and successful on-silicon program execution at 25~MHz is demonstrated. The initial board-level bring-up environment and test results are also presented, together with the observed limitations and the methods used to mitigate them.

ABSTRACT. On an MCU, an accelerator usually has its own arithmetic unit. This paper presents RFCA, which adds an ML accelerator to a single-core RISC-V MCU without adding any arithmetic, by letting it borrow the CPU's own fused multiply-add (FMA) unit. Two RTL modules are inserted into an X-HEEP SoC that uses a CV32E40P core with the FPnew FPU. A small arbiter shares the pipelined FMA with the accelerator cycle by cycle and routes each result back to its owner by the FPU's tag, so the pipeline is never drained. The accelerator, fed by the DMA of X-HEEP, streams a batched matrix product through the shared unit. On LeNet-300-100, it costs 1.12 cycles per multiply-add at every FMA pipeline depth from zero to five stages and runs 3.36 times faster than the CPU, with bit-identical results. Under CPU-strict arbitration, a concurrent FIR filter slows by 8 to 9 percent at every depth, and the accelerator by at most 0.15 percent. The accelerator also runs the MLPerf Tiny ResNet-8 network 3.12 times faster than the CPU, again bit-identical. In 40 nm synthesis, sharing adds 7.0 kGE of logic, 3.9 times less than an estimated accelerator with its own FMA, and gate-level analysis shows 27 percent lower inference energy than the CPU.

ABSTRACT. Aging-induced device degradation can progressively affect the performance and reliability of high-speed receivers. An Aging Performance Monitor (APM) for detecting and tracking receiver degradation throughout its operational lifetime is proposed. The APM independently monitors critical parameters, including gain, bandwidth, and jitter, and compares their degradation with predefined performance thresholds. Aging-aware simulations demonstrate that the proposed APM accurately follows different parameter degradation trends and identifies threshold crossings. The resulting monitoring information can be used for subsequent adaptive compensation, providing a basis for closed-loop aging-aware receiver operation.

ABSTRACT. Routing is one of the most time-consuming stages of physical design and negotiated-congestion routers depend on hand-tuned decisions such as the net order and the congestion penalty schedule. This paper reports a controlled study of three machine-learning components that supply these decisions with an unchanged A* rip-up-and-reroute kernel: a convolutional neural network (CNN) congestion prior, a gradient-boosted net ranker and a Q-learning schedule controller (together ML-NC). They are evaluated on synthetic grids of 32×32 to 64×64 GCells at three loads and on 29 windows cut from four public ISPD 2007 global routing benchmarks. Compared with a baseline whose schedule was set by hand, ML-NC lowers the overflow after five iterations by 23% on the nominal 48×48 designs, but all variants approach a similar overflow floor, so the gain is faster convergence rather than a better final solution. When the baseline schedule is re-tuned on 24 further designs it reaches a lower final overflow than every learned variant (ML-NC is 18% worse); the CNN prior used together with the re-tuned schedule still lowers the five-iteration overflow by 39% without a significant change of the final overflow. On the ISPD windows the learned components lower the five iteration overflow by 7% but do not improve the final overflow significantly. The study uses a Python two-dimensional router instead of an industrial one; it therefore demonstrates early convergence benefits and documents where the learned components do not help.

ABSTRACT. This paper proposes an adaptive stress redistribution technique for improving the long-term reliability of analog CMOS integrated circuits. The proposed architecture employs reconfigurable transistor banks and a stress-aware selection controller to reduce uneven degradation caused by prolonged electrical stress. Unlike conventional static redundancy or periodic switching approaches, the proposed method considers the predicted influence of transistor degradation on circuit-level performance when selecting the active transistor bank. A CMOS operational transconductance amplifier is considered as a representative implementation. The proposed architecture is designed to redistribute operating stress while preserving analog performance requirements, including gain, bandwidth, offset voltage, and power consumption. A validation methodology combining transistor-level aging simulations, process variability analysis, and Monte Carlo evaluation is developed to assess reliability improvement and implementation overhead. Simulations compare the proposed architecture with conventional and fixed-rotation designs in terms of gain, bandwidth, offset, and offset variability. The study aims to establish a circuit-level reliability improvement strategy for analog CMOS designs.

ABSTRACT. The rise of IoT and edge computing demands ultralow-power embedded processors. While dynamic power re- mains the primary energy bottleneck, conventional optimization methods often target only a single abstraction level, limiting potential energy savings. To address this, this paper investi- gates the impact of design modifications on power consumption across multiple abstraction levels. Using the open-source AFTAB RV32IM RISC-V core, we present a hierarchical design space exploration across the microarchitecture, register-transfer level, and gate level. By evaluating various architectural configurations and structural optimizations—including arithmetic unit topolo- gies, operand isolation, and clock gating—we analyze how cross- layer design decisions collectively influence power, area, and timing. Experimental results demonstrate that this multi-level investigation achieves significant dynamic power reductions while maintaining performance constraints, proving that a coordinated hierarchical approach is far more effective than isolated single- level techniques.

ABSTRACT. Stringent power, area, and throughput constraints in modern digital signal processing (DSP) and machine learning (ML) applications intensify the need for efficient, multi-function arithmetic hardware accelerators. To address these challenges, this paper presents a unified, run-time configurable floating point CORDIC accelerator capable of executing multiplication, division, sine, and cosine within a single shared datapath. Unlike conventional designs that rely on dedicated algebraic multipliers or fixed-precision structures, our approach integrates linear and circular operations into a common 68-bit register-accumulator framework supporting Half, Single, Double, and Extended IEEE 754 formats. By employing a spatially unrolled datapath, Kogge Stone prefix adders, fixed-offset logarithmic barrel shifters, and residual-based early termination, the architecture achieves a flex ible trade-off between numerical precision and latency. Evaluated in a 45-nm CMOS technology, the accelerator operates at 142.86 MHz and reduces average execution latency by 2.47× through dynamic precision scaling, demonstrating a high-performance and area-efficient solution for edge computing systems.

ABSTRACT. Electronics designed for use in radiation-harsh environment usually undergo rigorous testing before its deployment. One of the effects causing device malfunctions is Single-Event Latchup (SEL) caused by high-energy particles. A key factor influencing the tolerance of circuits to SELs is the power supply voltage. In this work, we experimentally evaluated the influence of power supply voltage on the occurrence of laser-induced SELs in a phase-locked loop circuit manufactured in IHP’s 130 nm BiCMOS technology. We experimented with the power supply voltages ranging from 2.2 V up to 3.6 V and an 808 nm laser. Our results show that a decrease in power supply voltage reduces the susceptibility of a circuit to SELs, whereas its increase makes the circuit more vulnerable.

ABSTRACT. Organic Light-Emitting Diode (OLED) technology represents a significant advancement in display systems, offering superior image quality, energy efficiency, and design flexibility compared to traditional Liquid Crystal Display (LCD) technology. However, manufacturing complexity, material degradation, high production costs, and limited lifespan present substantial barriers to widespread adoption. This paper examines strategic innovation approaches employed by three leading manufacturers to overcome these challenges. Through case study analysis, Samsung Display's specialization in small-to-medium Active-Matrix OLED technology, LG Display's advancement in large-format panels with AI-integrated manufacturing, and BOE Display's flexible display innovations are investigated. Results demonstrate that differentiated strategies enable market leadership in distinct segments. Samsung achieved dominance in mobile displays through early investment and process optimization. LG reduced production time from three weeks to two days via AI implementation. BOE successfully entered the market through flexible AMOLED technology. These approaches collectively accelerated OLED maturation and established pathways for next generation display infrastructure development.

ABSTRACT. Three-dimensional vertical NAND (3D V-NAND) flash memory represents a transformative advancement in semiconductor technology, addressing critical limitations of planar NAND scaling below 20nm nodes. Traditional two-dimensional architectures face severe challenges including program noise, time-dependent threshold voltage instability, and cell-to-cell interference that compromise reliability and performance. This paper examines the architectural evolution from planar to vertical structures and analyzes strategic engineering decisions by major manufacturers including Samsung, SK Hynix, Micron, and Kioxia. Key innovations include the transition from gate-first to gate-after processes, implementation of CMOS-under-array (CuA) integration techniques, and advanced bonding technologies such as Bonding Vertical NAND (BV-NAND) and CMOS Bonded Array (CBA). Comparative analysis demonstrates substantial progress from 2019 to 2026, with recent devices exceeding 400 wordline layers, achieving bit densities up to 29 Gb/mm² and I/O speeds up to 5.6 Gb/s. These architectural innovations enable continued density scaling beyond lithographic limits, supporting increasing storage demands in artificial intelligence infrastructure and establishing 3D V-NAND as essential for next-generation memory hierarchies.

ABSTRACT. The transition to chiplet-based system architectures introduces critical new challenges, one of which is a die- to-die (D2D) interconnect test and repair. Unlike traditional monolithic designs, multi-die systems must ensure D2D interface integrity, a requirement that becomes increasingly critical as aggressively scaling interconnect density and complexity drive the adoption of new emerging technologies. This study presents a comprehensive investigation into D2D interconnect testing by systematically analyzing the relationship between physical defects, fault manifestations, and current test methodologies. We establish a taxonomy of interconnect types and defect mechanisms, characterize their electrical behavior under varying conditions, and evaluate modern test strategies, including deterministic and layout-aware approaches. Our findings demonstrate that effective D2D interconnect testing necessitates an integrated framework combining defect physics, fault modeling, and practical test techniques, elements essential for achieving reliability and quality in the emerging chiplet-based ecosystem.

ABSTRACT. Cross-technology migration of analog circuits faces the fundamental challenges of scarce target-technology data and distribution shifts between source and target domains. This paper proposes PAC-GAT, a physics-aware transfer learning framework that jointly encodes circuit topology via graph attention networks and integrates gm/Id-inspired physical features. The proposed Physics-Aware Connected (PAC) framework is evaluated on two op-amp topologies across different technology nodes, where only uses 1,000 fine-tuning samples (10% of source domain sample size) from the target domain set and achieves blind testing on a 10,000-sample hidden dataset. On a five-transistor op-amp, PAC-GAT achieves MAPE below 1% for phase margin (0.11%) and slew rate (0.80%), and around 1% for DC gain (1.04%). On the more complex two-stage Miller-compensated op-amp, it delivers up to 2.3× accuracy improvement over the baseline. The PAC method achieved leading prediction performance on the official independent hidden test set of the 2025 EDA Elite Challenge benchmark, validating the method’s generalization capability in practical design-migration settings.

ABSTRACT. Formal equivalence checking is increasingly used as the correctness judge for Verilog written by large language models, yet the behaviour of the oracle itself is rarely reported. We measure it. Using one open-source flow (Yosys 0.69, miter plus SAT) with a two-tier protocol, a bounded check from the reset state followed by a temporal-induction proof, we judged 8,385 candidate-versus-golden pairs drawn from VerilogEval v2 and RTLLM v2.0: 1,259 testbench-passing designs produced by two models, 5,353 source-level mutants and 1,773 synthesis-level mutants of the goldens. Overall, 2.1 percent of checks (95 percent CI 1.8 to 2.4) end without a conclusive verdict; for generated designs the share is 3.4 percent (2.5 to 4.6). Of 2,028 equivalences, 90.7 percent (89.4 to 91.9) are proven by induction and the remainder are bounded to 30 cycles; every bounded verdict falls on a sequential design (188 of 1,121 sequential equivalences versus 0 of 907 combinational ones). Raising the solver budget from 120 to 600 seconds resolved 71 of 98 timeouts, at a cost of 5.7 hours of unattended solving for 0.8 percent of the population. We quantify three pitfalls of a naive flow: an induction-only check that can report power-on differences unreachable by any testbench, a SystemVerilog construct that silently turned 31 generated designs and 225 mutants into tool errors, and interface width disagreements that simulation tolerates but the miter refuses (15 of 1,259 designs). We recommend reporting the verdict lattice, not a pass rate, whenever formal equivalence scores generated hardware.

ABSTRACT. Abstract—Closed-loop visual tracking on a moving pan-tilt- zoom mount faces a coupling image-space trackers cannot resolve: apparent image-plane motion is the sum of the target’s motion and the platform’s own slew. The conventional remedy estimates both and subtracts, which sums two estimator variances and injects a slew-correlated bias whenever the filters differ in group delay. We remove the coupling at measurement formation instead. Each detection becomes an absolute pointing angle, the mount angle interpolated to the frame’s capture instant plus the pixel offset mapped through the field of view, so platform motion enters additively and cancels identically, and one Kalman filter replaces two filters and a difference. Sensor physics then dictates an asymmetric filtering policy: the 14-bit absolute encoder quantizes to 0.67 px, so that channel is left unfiltered while the vision channel is filtered. On an NVIDIA Jetson Orin NX, a systematic sweep reduces RMS centring error from 33.5 to 10.0 px on a 35◦ /s orbit and improves all six trajectory families tested, from −29% to −78%, with lag falling alongside accuracy. Two measured identities explain the operating point: the per- axis pixel gains are one physical loop gain of 1.85 s−1 , their asymmetry being the gear ratio, and the feed-forward lead that nulls lag is the closed-loop time constant 1/K rather than the transport delay. Lag is therefore gain-limited, and the gain ceiling follows from loop delay. Index Terms—

ABSTRACT. Robust unmanned aerial vehicle detection under changing illumination and complex backgrounds can benefit from combining visible and infrared information. Although RGB-IR detectors commonly employ multi-scale feature fusion, fusion at every available feature-pyramid level increases the number of cross-modal operations and does not necessarily provide equal contribution to detection performance. This paper evaluates the influence of feature-pyramid level selection in a modified dual-stream RGB-IR UAV detection architecture. Feature representations extracted at the P3, P4, and P5 pyramid levels are selectively fused using a fixed channel-concatenation operation followed by 1x1 projection. Six configurations are evaluated, including individual P3, P4, and P5 fusion, two-level P3+P4 and P4+P5 fusion, and full P3+P4+P5 fusion. The Anti-UAV dataset is used for model training and evaluation under identical preprocessing and optimization settings. The results indicate that feature-pyramid levels contribute differently to multispectral detection. Full P3+P4+P5 fusion achieves the highest overall accuracy, while P3+P4 fusion provides closely comparable detection performance with fewer cross-modal fusion operations. The findings demonstrate that selective feature-pyramid fusion can provide a favorable balance between detection accuracy and model complexity.

ABSTRACT. Conventional failure-analysis flows rely on extensive manual configuration, simulation setup, defect injection, and post-processing, resulting in long turnaround times and increased susceptibility to human error. This work presents an end-to-end automated workflow that integrates configuration management, automated netlist generation, streamlined defect-injection, SPICE-level simulation execution, and systematic extraction and classification of fault behaviors. The proposed method enables fast, repeatable inductive fault modeling while significantly improving result consistency. Experimental results show significant reductions in total analysis time and measurable gains in defect-coverage metrics, making the methodology scalable to large defect sets and suitable for advanced memory technologies.

ABSTRACT. 3DIC routing is one of the most important problems in modern VLSI design. TSV assignment is a core stage in this process. It maps inter-die nets to candidate TSV sites in order to minimize total wirelength. There are many methods proposed for the TSV assignment problem. Most of them are based on sequential heuristics or machine learning approaches. In this paper we propose a SAT-based TSV assignment algorithm which solves the problem globally and provides optimal results. This is the first work applying a MaxSAT solver to the TSV assignment problem. We formulate the problem as a Weighted Partial MaxSAT instance and use OLL and LinearSU solvers adaptively. Experimental results on eight synthetic benchmarks show wirelength improvement over the SBMI baseline in all cases. On floating feedthrough designs the improvement ranges from 18% to 63% and on non-floating designs the improvement is between 2% and 9%. All solutions are proven optimal.

ABSTRACT. Address decoders are among the simplest blocks of a digital system and among the most decisive for its speed: a memory, a register file or a data converter can be accessed no faster than its decoder resolves an address. The flat decoder, which forms every one-hot output as a single minterm of the address bits and their complements, has the smallest possible logic depth and is therefore the intuitive choice for high-speed operation. Its price is fan-out: each address rail must drive half of the output gates and span the whole output array physically. In this work the hierarchical decoder is treated not as an independent alternative but as a transformation of the flat one. A restructuring procedure is defined that partitions the address vector into groups, replaces the single level of wide minterm gates by a set of predecoders and a regular final AND grid, and preserves the input/output interface exactly. The procedure is applied to a 4-to-16 decoder, and the flat reference together with the restructured version is carried through an identical 14 nm standard-cell flow: synthesis, floorplanning, placement, clock tree synthesis, routing, parasitic extraction and post-layout static timing analysis. Restructuring lowered the worst-case propagation delay from 0.82 ns to 0.68 ns, raising the equivalent maximum operating frequency from 1.22 GHz to 1.47 GHz, and lowered power from 96 μW to 89 μW, at the cost of 8.6 % additional cell area. The measurements show that what limits a flat decoder after layout is fan-out and rail length, not logic depth.

ABSTRACT. Partitioning large circuits into balanced subcircuits is essential for parallel and distributed simulation. Conventional graph-partitioning methods primarily consider structural connectivity, while learning-based approaches do not always account for the electrical significance of circuit branches. This paper extends the Generalizable Approximate Graph Partitioning (GAP) framework to weighted circuit graphs by incorporating edge weights into GraphSAGE-based message passing and introducing a differentiable weighted-cut objective alongside the balancedness and topology-based normalized-cut terms. The proposed model is trained on synthetic weighted graphs and evaluated against METIS on previously unseen graphs of varying sizes and partition counts. Experimental results demonstrate that the method maintains nearly balanced partitions and achieves normalized-cut values generally comparable to METIS, including on graphs exceeding the maximum training graph size. In terms of computational efficiency, the proposed method achieves lower runtime than METIS on five of the seven test graphs, with a 1.51-2× speedup for graphs containing 1024-10000 nodes. These findings indicate the potential of the proposed approach for inductive weighted circuit partitioning, although improvements in weighted-cut minimization and large-graph inference efficiency remain necessary.

ABSTRACT. Efficient execution of deep neural network inference on edge platforms requires minimizing software overhead while maintaining high accelerator utilization. This paper presents a hybrid hardware--software scheduling architecture for a configurable general matrix multiplication (GEMM) accelerator integrated within a system-on-chip (SoC) for edge AI applications. The proposed system-on-chip integrates a RISC-V processor with a dedicated matrix multiplication unit, a hardware scheduler, and a lightweight dispatcher to automate execution of tile-based matrix operations with minimal CPU intervention. The scheduler partitions matrix operations into tiles and coordinates data movement and computation, while the dispatcher manages execution and buffering. To further improve efficiency, the design incorporates a shape-aware DMA engine with integrated computation mapping, zero-injection logic that eliminates software-based padding, and a ping-pong buffering mechanism that overlaps data transfer with computation. Experimental evaluation using multilayer perceptron (MLP) workloads demonstrates a peak performance of 3.2 GOPS, with roofline analysis identifying memory bandwidth as the primary performance bottleneck. ASIC synthesis in 45 nm technology demonstrates that the dispatcher adds only 5.1% area and 2.9% power overhead relative to the accelerator. The results indicate that hardware-assisted scheduling and dispatching can substantially reduce CPU involvement in accelerator execution with negligible hardware cost.

ABSTRACT. Abstract — Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) devices use a high electron mobility channel that gives fast switching and low power loss. This work presents Sentaurus TCAD based research for normally OFF pGaN Gate HEMTs. The pGaN Gate HEMT adds a p-type GaN layer under the gate to make the transistor normally-off. The pGaN layer depletes the 2DEG under the gate at zero bias which means it stays safe, does not conduct when no gate voltage is applied and offers better control. For capturing real-world behavior, the following physics models included drift-diffusion transport, bandgap narrowing, tunneling effects and polarization models. As result, the breakdown voltage was 278.04 V and Ids = 0.28 A maximum current in Vgs = 5 V.

ABSTRACT. The impact of substrate metals on the breakdown voltage of p-GaN gate High Electron Mobility Transistors (HEMTs) is presented with different substrate metals Si, Al₂O₃ and 4H-SiC. As the gate is placed on top of the AlGaN/GaN layer, p-GaN gate HEMTs include a p-GaN layer under the gate to make the transistor normally-off. Drain voltage sweeps in the off-state condition revealed breakdown voltages of 277.89 V on Si, 286.11 V on Al₂O₃, and 271.86 V on 4H-SiC, demonstrating variations of approximately 5–6% across the substrates. These results highlight that substrate selection plays a mandatory role in determining static BV for p-gate GaN.

ABSTRACT. Surgery for endometrial cancer carries considerable perioperative risk, yet standard risk assessment approaches may fail to fully account for the intricate interplay of clinical, metabolic, inflammatory, and pathological variables. This study introduces a multimodal machine learning framework designed to predict perioperative risk on a personalized basis for patients undergoing endometrial cancer surgery. The framework combines four distinct data modalities and employs median imputation, one-hot encoding, z-score normalization, feature engineering, and correlation-based feature selection. Five classifiers–Random Forest, XGBoost, LightGBM, CatBoost, and Support Vector Machine–were assessed through stratified 10-fold cross-validation paired with Bayesian hyperparameter optimization. In experiments involving 150 patients, XGBoost emerged as the top performer, reaching an accuracy of 0.887, an F1-score of 0.867, and an ROC-AUC of 0.926. Fusing multiple modalities increased the ROC-AUC from 0.812 with clinical variables alone to 0.926 for the full model. SHAP analysis additionally revealed important metabolic, inflammatory, comorbidity, and pathological predictors, enabling interpretable and personalized stratification of patients into low-, moderate-, and high-risk categories to support clinical decision-making.

ABSTRACT. Complete cytoreduction is the single strongest modifiable prognostic factor in advanced epithelial ovarian cancer (EOC), yet more than 70% of patients present at FIGO stage III–IV, where preoperative assessment of surgical resectability remains largely subjective. Inaccurate assessment leads to non-therapeutic laparotomies, delayed systemic therapy, and worse outcomes. This paper proposes a multiparametric machine-learning framework that fuses clinical, laboratory, radiological, morphological, and molecular-biological features into a unified model of the probability of complete cytoreduction, and uses this prediction to personalize the choice between primary debulking surgery (PDS) and neoadjuvant chemotherapy (NACT). We introduce the Integrated Resectability Risk in Ovarian Cancer (IRRO) index, an ensemble-derived, calibrated score that stratifies patients into high-, intermediate-, and low-surgical-potential groups. The framework couples tree-based ensembles (Random Forest, Gradient Boosting, XGBoost) with a multilayer neural network and model-agnostic interpretability, and is formalized here as an explicit mathematical pipeline and evaluated on a cohort of 1500 advanced-EOC patients (a 300-patient held-out test set) treated in specialized oncology centers of the Republic of Uzbekistan. On the held-out test set, the calibrated IRRO ensemble achieved the highest discrimination among the compared models (AUC 0.878), exceeding every individual base learner. We describe the feature taxonomy, the model equations, the IRRO construction, and a rigorous evaluation protocol–discrimination, calibration, and survival analysis–benchmarked against established resectability indices. The resulting clinical decision-support system aims to operationalize personalized treatment planning in advanced EOC.

ABSTRACT. Accurate delineation of tumor regions in mammography images is a key prerequisite for computer-aided diagnosis of breast cancer, yet it remains difficult because lesions are often small, low-contrast, and embedded in dense fibroglandular tissue. This paper presents a lightweight U-Net-based architecture designed to segment tumor regions from the surrounding breast tissue with high accuracy and a reduced parameter budget. Three components are combined. First, full-scale skip connections let every decoder stage fuse low-level spatial detail transferred from the higher-resolution encoder stages through max-pooling with high-level semantic information transferred from the deeper decoder stages through Lanczos interpolation, which preserves the boundaries of small objects that a plain encoder–decoder tends to lose. Second, a classification-guided module derived from the deepest encoder stage predicts the presence or absence of a lesion and multiplies its decision into the segmentation map, suppressing false-positive responses in tumor-free images. Third, a three-level hybrid loss that couples focal loss, a multi-scale structural similarity (MS-SSIM) term, and an IoU term sharpens the predicted mask at the pixel, patch, and map levels. Trained and evaluated on a corpus aggregated from publicly available mammography datasets, the proposed model reaches a validation Dice coefficient of 0.68, exceeding the best baseline value of 0.60 reported in the literature, while keeping the per-scale channel count low. The total number of parameters is 39,619,393 (151.14 MB), of which 19,585,409 (74.71 MB) are trainable.

ABSTRACT. AI agents call services on behalf of users and delegate parts of their tasks to sub-agents, so every call needs a narrow, verifiable permission. The common online approach asks the authorization server about each request (OAuth 2.0 token introspection), which makes the server a dependency of every call. We compare it with offline-verifiable authorization: the user's grant is a Biscuit token that the service's gateway checks locally with only the issuer's public key, and that agents attenuate for sub-agents without contacting any server. Both designs share one gateway implementation that differs only in the authorization check. Under injected authorization-server faults (errors, hangs, a frozen process, flapping), the offline gateway kept serving 100% of requests while the online gateway refused almost all of them for the duration of the fault. An introspection cache helped the online gateway only until its entries expired: with a 5 s TTL it served 7-19% of requests during a 20 s fault (median of 5 runs). When agents delegated to new sub-agents during the fault, offline agents completed every task and online ones 0.3-0.4%, with or without a cache. The price of going offline is revocation lag bounded by the revocation-list refresh interval, the same trade-off an introspection cache makes. In steady state the offline check is also cheaper: 0.19 ms against 1.07 ms for introspection at 200 req/s, and end-to-end p99 1.77 ms against 2.88 ms.