ABSTRACT. This paper presents the results of comparative investigation of the Adaptive Antenna Arrays (AAAs), that are used as antennas of the Global Navigation Satellite System receivers. Four different configurations of a circular AAA as well as four configurations of a cylindrical AAA are considered. Each AAA consists of 9 antennas, where the 9-th antenna is the reference one. A single reference antenna can also be replaced with a co-phased array of 4 antennas. The reference antenna is either placed at the phase center of the AAA, which is also the geometrical center of the circle or cylinder, or it is raised above the AAA center on the distance of one wavelength of the carrier signal. The investigated type of the AAA is the interference canceller. The square root free QR decomposition Recursive Least Squares adaptive filtering algorithm is used for the calculation of the AAA weights. Simulation demonstrates an advantage of the AAAs with a co-phased AA as the reference antenna, the advantage of AAA with a raised reference antenna and the advantage of the cylindrical AAA compared to other versions of the considered AAAs. The comparison has been done in terms of the steady-state interference suppression ratio, in both graphical and numerical data obtained by averaging over 100 statistically independent simulation experiments. The experiments differed by the locations of the interfering signal sources.

ABSTRACT. Routing a 3D integrated circuit must connect every net around the obstacles on each die and across the dies’ through silicon vias. A 3D IC router for this flow is presented, covering LEF and DEF parsing, through-silicon via assignment, per-net Steiner tree construction, congestion-aware global routing, and detailed routing. For Steiner tree construction, the router uses FLUTE for small nets. For nets above a fixed pin-count threshold, this paper proposes an obstacle-avoiding Steiner tree construction algorithm, OAST, in a two-dimensional version OAST 2D and a three-dimensional version OAST 3D. Both build a candidate graph with an obstacle-aware sweep based on Zhou’s rectilinear spanning graph, then connect pins with standard shortest-path and minimum-spanning-tree techniques. OAST 3D also uses each pin’s real metal layer and real per-layer obstruction data. Over a set of synthetic test cases, the median wirelength reduction for large nets against the FLUTE-based baseline is 7.8% for OAST 3D and 7.1% for OAST 2D. OAST 3D improves on OAST 2D by a median of 0.9%.

ABSTRACT. Growing code size increases the ROM and Flash requirements of resource-constrained embedded systems. To address this challenge, we propose a RISC-V instruction compression technique in which a Python-based post-processing tool rewrites the precompiled program image, replacing the opcode and function fields of a 32-bit instruction with Huffman codes generated from instruction frequency information. On the hardware side, a small two-step decoder uses the Huffman group code and index to reconstruct the standard 32-bit instruction word, reusing the core's original execution logic. The design is evaluated on nine benchmark tests from riscv-tests running on the modified FemtoRV32 Gracilis core, which is referred to as the HuRV (Huffman-coded RISC-V) core, against the baseline FemtoRV32 Gracilis core running the original code. Since the benchmarks are small, their program images are scaled to 64 KB for the area evaluation. Experimental results show an average code size reduction of 6.59% beyond the compression already provided by RVC, and 5.0% fewer execution cycles on average. When synthesized using SKY130 technology with OpenRAM ROM macros, the ROM area was reduced by 6.22% on average while the core area grew by 3.3%, giving a 4.93% smaller core and ROM combination. The area savings are positive for every benchmark, from 3.8% to 5.6%. The technique provides a practical way to further reduce code size beyond RVC while keeping the hardware implementation simple.

ABSTRACT. Integrated circuits (ICs) grow by their integration levels every year, and the associated timing optimization is increasing in complexity. [3] Therefore, timing optimization will continue to be essential for this reason [3]. In general, the accurate timing evaluation involves synthesis and then timing analysis. [1, 2]. Therefore, several methods have been suggested to directly predict timing metrics from RTL [1, 2]. A timing-prediction model created for a particular standard-cell library will require a new set of data and the model must be retrained when the target library changes [3, 7-9]. Many syntheses and timing-analysis runs may be performed to gain an understanding of the costs and engineering effort required to perform thousands of syntheses and timing-analysis runs [1, 2]. Despite the extensive research on RTL timing prediction, most studies compare accuracy of prediction across different technologies with little attention paid to generalization across technologies [1, 2, 5]. For this reason, the cross-technology transferability of RTL timing-prediction models are explored, and the feasibility of using a small data set from a target technology to improve prediction accuracy on a technology node that has not been previously encountered is investigated. The neural-network models were designed and trained to forecast the slack for the critical paths on designs built using SAED14nm and SAED5nm standard-cell libraries. For the SAED14nm timing predictor, the training set consisted of all the SAED32nm designs, and 30% of SAED14nm designs, with the remaining 70% of the SAED14nm designs used for testing purposes. The model achieved an R² of 0.86, an MAE of 0.041778 nanoseconds (ns), and an RMSE of 0.0892 ns. The training set for SAED5nm timing predictor consisted of all SAED32nm designs and 25% of all SAED5nm designs. This model achieved an R² of 0.9249, an RMSE of 0.089909 ns, and an MAE of 0.056154 ns. The results of the experiments reveal that data learned from 32 nanometer (nm) designs can be effectively transferred to advanced technology nodes. The results showed that 25-30% of the target-technology training level samples achieved significantly higher prediction accuracy than direct cross-technology transfer.

ABSTRACT. On edge and tiny machine learning (TinyML) hardware, neural inference must be fast and exact within small logic and power budgets. Small custom instructions on fieldprogrammable gate array (FPGA) soft processors are a low-cost route, but their benefit is seldom resolved layer by layer, and it is rarely clear how much of it comes from the datapath and how much from the firmware around it. This paper presents a layer-aware hardware/software co-design, using an 8-bit integer (INT8) convolutional neural network (CNN) for MNIST digits as a controlled case study. A custom function unit (CFU) provides a four-way INT8 multiply-accumulate (MAC4) and a fourinput maximum (MaxPool4), the firmware restructures operand layouts, and requantization stays in software. Six per-layer CFU functions are then consolidated into three shared ones. The design runs on a VexRiscv RISC-V core at 75 MHz on a Nexys A7-100T board. On the board, every layer output of the evaluated test input matches the reference bit for bit, and one inference takes 6,658,981 instead of 17,267,763 cycles, a 2.59× speedup (61.4% fewer cycles). Consolidation halves the function count; reported system totals fall from 5,480 to 4,671 lookup tables, although most of this change lies outside the CFU. The per-layer data show that on this platform the code around each custom instruction, not the one-cycle datapath, limits the gain.

ABSTRACT. Hospitals without a structured health record keep cancer treatment histories in word-processor forms, one discharge summary (epicrisis) per hospitalization or chemotherapy course. Turning them into a database can go wrong in two independent ways: the extractor may misread a correct document (a parser fault), or it may correctly read a document that is itself wrong (a document fault). We study both on Armenian epicrises from an oncology service. A rule-based form parser, which reads the Word structure including bold selections, superscripts and legacy-font text, reached 99.7% field accuracy on 34 anonymized documents, against 82.2% for a 12-billion-parameter LLM running locally on a consumer GPU when given formatting-aware text and 80.7% when given plain text. The gap was largest on options that are selected only by bold type (100.0% vs 91.2% vs 9.8%). Because each form is made by saving over the previous one, values are carried forward without being updated: stay dates, hospitalization numbers, lab panels under new dates and untouched template defaults. Consistency checks over each patient's series of documents reported all 20 copy-forward faults documented by hand in a 32-course series, with 1 of 28 warnings not matching a documented fault. Extraction accuracy alone therefore overstates data quality; both kinds of fault need their own test.

ABSTRACT. Thin-oxide transistors enable compact, high-performance transmission gates but may exhibit significant leakage, particularly under standby conditions and across process, voltage, and temperature variations. This article examines design techniques for minimizing leakage current in thin-oxide transmission gates while preserving acceptable switching performance. The approach considers complementary nMOS–pMOS control, series stacking, transistor sizing, and body-bias adjustment were supported by the target process. It also distinguishes subthreshold leakage from gate-tunneling leakage, since techniques effective for one component may not adequately reduce the other. The design trade-offs among leakage, on-resistance, delay, area, and oxide reliability are discussed, emphasizing that the optimal implementation depends on the target process and operating conditions. The article provides a practical framework for selecting and verifying leakage-reduction techniques through circuit simulation across relevant operating corners.

ABSTRACT. The proposed paper examines the application of robotics in logistics systems, with a particular focus on path‑planning methods. Drawing on twenty recent studies, it explores classical algorithms such as A* and Dijkstra, sampling‑based approaches like RRT*-Connect, chaotic models using logistic maps, and advanced AI‑driven techniques including transformer‑GCN integrations. The analysis highlights strengths and limitations of each method, from reliability and transparency to adaptability and scalability. Special attention is given to multi‑robot coordination, ROS‑based frameworks, and vision‑driven navigation. The study concludes that hybrid models combining classical robustness with AI adaptability represent the most promising direction for future logistics robotics.

ABSTRACT. The evolution of advanced process technologies has driven continuous growth in the scale of very large-scale integration (VLSI) layouts. The massive number of geometric objects imposes significant computational performance bottlenecks on traditional physical verification methods. A large number of spatial relationship queries among layout objects further increase the computational overhead, making geometric query efficiency a critical factor in large-scale layout analysis. To address this issue, this paper presents a comparative analysis of six spatial index structures---prefix scan, quadtree, sweep-line interval tree, quadratic-split R-tree, incrementally inserted R*-tree, and bulk-loaded R*-tree---within a unified parallel connectivity-tracing framework. Experiments are conducted on three industrial layouts of different scales, ranging from 63.7~MB to 5.42~GB, with build time, query time, and peak memory measured under an 8-thread parallel environment. The results show that all six indexes produce consistent geometric connectivity-tracing results. On the largest 5.42~GB layout, the bulk-loaded R*-tree achieves a build time of 5.11~s, a query time of 20.2~s, and a peak memory of 15.70~GB, demonstrating favorable overall performance under the test settings of this paper. The results indicate that for static, large-scale, read-only VLSI layout tracing tasks, the bulk-loaded R*-tree achieves a favorable balance among build cost, query efficiency, and memory consumption.

ABSTRACT. This paper investigates the application of supervised machine learning methods to the design of electromagnetic systems. Two types of electromagnetic devices are considered: a straight-armature electromagnet and an electromagnetic brake incorporating magnetorheological (MR) fluid. Computational databases containing 999,959 and 642,600 unique design configurations, respectively, were generated using previously developed automated design systems. These databases were used to train and evaluate classification and regression models. Classification models were developed to assess device operability based on the permissible control-coil temperature. For the straight-armature electromagnet, the Decision Tree Classifier achieved a training-set accuracy of 99.9974%, while for the MR-fluid electromagnetic brake, the Random Forest Classifier achieved 99.9872%. Regression models were developed to predict the main design and operating parameters of the investigated devices. The MLP Regressor provided the best reported performance for the straight-armature electromagnet, while the Gradient Boosting Regressor performed best for the MR-fluid electromagnetic brake. For the straight-armature electromagnet, the average prediction time was 0.0003 s, approximately 400 times shorter than the corresponding conventional calculation time. The results demonstrate the potential of machine learning methods to accelerate electromagnetic design calculations through operability assessment and parameter prediction within the investigated computational datasets.

ABSTRACT. This paper investigates the influence of nonuniform winding distribution of a control coil on the magnetic characteristics of a lifting electromagnet using a distributed magnetomotive-force magnetic equivalent circuit model. The previously developed model is extended by introducing a generalized representation in which the local magnetomotive force is determined by the local number of winding turns. Uniform, linear-gradient, centered localized, and spatially shifted localized winding distributions are considered within a unified parametric framework. The effects of the magnitude, width, and position of winding nonuniformity are evaluated at low, nominal, and saturation-sensitive magnetic loading levels. The results show that the electromagnetic response depends strongly on both the spatial pattern and the location of the winding redistribution. Linear turn-density gradients produce the largest variations, with the maximum relative change in the required total magnetomotive force increasing from approximately 0.24 percent at low loading to 0.50 percent at the nominal operating point and 0.71 percent under saturation-sensitive conditions. The maximum local flux-density deviation reaches approximately 1.52 percent. Shifted localized nonuniformities also show pronounced position-dependent effects, whereas centered localized variations and changes in their width have substantially smaller influence. The results demonstrate that relatively small changes in the total excitation requirement may coexist with more pronounced local magnetic-field redistribution and that both global and local magnetic quantities should be considered when assessing winding nonuniformity.

ABSTRACT. The two most used benchmarks for LLM-based Verilog generation, VerilogEval v2 and RTLLM v2.0, score a generated design by running the benchmark's own reference testbench. We audit those testbenches without using any model output. For each of 179 designs we synthesize the reference implementation with Yosys, inject up to ten single-cell netlist mutations, remove the 127 mutants that are formally equivalent to the reference, and measure the kill rate of the reference testbench on the remaining 1,643 valid mutants. The pooled kill rate is 94.7 percent (95 percent CI 93.5 to 95.7); 81.6 percent of testbenches (75.2 to 86.6) kill every mutant and 3.4 percent (1.5 to 7.1) kill fewer than half. The corpora differ sharply: 89.4 percent of VerilogEval testbenches are complete against 51.4 percent of RTLLM testbenches, and RTLLM sequential designs are weakest (45.8 percent complete, mean kill rate 0.80). Testbench strength falls with design size (rank correlation negative 0.26) and is lower for sequential than for combinational designs. We also audit reference hygiene: 12 of 206 loaded items fail a self-check, among them two RTLLM references that fail their own testbench and one VerilogEval testbench that connects ports its reference lacks. Under the single-fault model, a testbench pass would accept a faulty design 5.2 percent of the time (3.3 to 7.4) overall and 16.5 percent (9.8 to 23.7) on RTLLM.

ABSTRACT. The Advanced Encryption Standard (AES) is ubiquitous, widely used in all kinds of secure embedded systems, from Internet of Things (IoT) devices to leading processors. The security of AES is under serious threat from side-channel attacks (SCA), in particular differential power analysis (DPA). The power consumption pattern of standard complementary metal-oxide-semiconductor (CMOS) submodules is consistent with sensitive data and is therefore predictable. This work proposes a hardware-level protection mechanism designed for Probabilistic Spin Logic (PSL). It introduces physical randomness into the calculations by replacing deterministic S-boxes with stochastic modules based on p-bits. This paper compares traditional approaches with the proposed new design, focusing on the analysis of the most important parameters.

ABSTRACT. Access control lists (ACLs) remain the dominant packet-filtering mechanism in enterprise networks, yet their first match, top-down evaluation semantics makes them structurally prone to logical anomalies that no router reports at configuration time. This paper presents a set-theoretic model of Cisco IOS extended ACLs together with a lightweight, dependency-free static analyser that detects shadowing and redundancy anomalies directly from unmodified show access-lists output. Each rule is treated as a hyperrectangle in the five-dimensional packet header space, and anomaly classification is reduced to a pairwise containment test combined with an action comparison. Ground truth is computed exactly, by subtracting all preceding rules from each rule's match set, rather than taken from the author's intent. On a 15-rule policy deployed on a three-zone Cisco Packet Tracer topology, the analyser finds all nine unreachable rules, whereas a baseline that ignores transport-layer ports reports three spurious rule pairs, one of which would delete a live SSH rule. On a benchmark of 600 synthetic policies of 50 to 2000 rules containing 54 933 unreachable rules, the port-aware analyser attains a precision of 1.00 at every size, against 0.59 for the port-agnostic projection; its recall of 0.93 measures the rules that are unreachable only through a union of predecessors. A 2000-rule policy is analysed in about 1.1 s. We position the analyser against Batfish, header space analysis and VeriFlow: it trades completeness for zero dependencies and direct auditability of device output. Correlation and generalisation anomalies are outside the present scope.

ABSTRACT. Card-based identification underlies access control, working-time recording and many related applications, yet reader terminals are commonly bound to a particular software platform. This paper describes the design, analysis and field deployment of a standalone NFC terminal based on the ESP32 microcontroller that can be attached to an arbitrary server. The terminal combines a PN532 reader, a W5500 Ethernet controller, an ILI9341 display and an RGB indicator, and exposes two open interfaces: a local HTTP API for discovery, provisioning, diagnostics and signed firmware updates, and an outbound HTTPS request whose response is rendered on the display. The firmware is organized as five Free RTOS tasks with exclusive ownership of each peripheral driver, which keeps the user interface responsive while the server is slow. We analyse the card latch that maps a physical card presentation to a single server request and derive a closed-form expression for the duplicate request rate, which agrees with a discrete-event simulation to within 3.5% for rates above 40 per hour. A conventional consecutive-miss latch discards a card presented within 765 ms of the preceding one; the UID-aware latch adopted in the firmware removes this loss while making identical decisions for a single card, as verified over 8×10exp6 randomized steps. Three terminals have been in operation for approximately eighteen months at a construction company and two supermarkets, where they serve 80 employees.

ABSTRACT. A nonlocal contact problem for the modified Helmholtz equation is considered in a rectangle divided by a contact line into two subdomains. Only continuity of the solution is required on the contact line, so the normal derivative may have a jump there, and the values of the solution on the contact line are related by a nonlocal condition of Bitsadze--Samarskii type to its values on two interior lines. A computational algorithm is proposed in which an outer iterative process reduces the problem to a sequence of independent Dirichlet problems in the subdomains. These problems are approximated by finite difference schemes on a grid aligned with the contact line and the lines of the nonlocal condition and are solved by the successive over-relaxation method with Chebyshev acceleration. The algorithm is implemented in Mathcad. A numerical experiment on a model problem with a jump of the normal derivative on the contact line shows second-order convergence both in the whole domain and on the contact line, and the number of outer iterations is practically independent of the mesh size.