ABSTRACT. In this paper, we present a signal integrity (SI) analysis and design guidance for chiplet interfaces based on the universal chiplet interconnect express (UCIe) standard, focusing on the interaction between routing topologies and meshed ground (M-GND) structures. Using full-wave electromagnetic simulations, we evaluate the channel loss and crosstalk (XT) based on the voltage transfer function (VTF), considering return path discontinuities modeled as mesh defect widths ranging from x0 to x9 relative to the signal width. Ground-signal (GS) topologies effectively suppress XT, but their performance degrades with return path discontinuities from meshed ground defects. Even under narrower line and space (L/S), increased conductor thickness improve channel loss and XT at high frequencies, while reducing sensitivity to ground variation. These findings support a robust interconnect design strategy for SI enhanced chiplet integration under practical packaging constraints.

ABSTRACT. In this paper, we conduct a signal integrity (SI) analysis for universal chiplet interconnect express (UCIe)-based high-speed interconnection, considering surface roughness. A simulation-based analysis is performed using the Huray surface model to investigate the effect of surface roughness. As surface roughness increased, voltage transfer function (VTF) exhibited a degradation of up to-2.785 dB at the Nyquist frequency. Consequently, the eye-height decreased by 12.3 % and the jitter increased by 6.1 %, leading to a violation of the universal chiplet interconnect express (UCIe) advanced package specification. Our work demonstrates the impact of surface roughness on SI in high-wire-density environments in chiplet interfaces with stringent design requirements and emphasizes the importance of incorporating realistic surface roughness conditions into the analysis for practical designs.

ABSTRACT. We propose Mem-Village, a hybrid high bandwidth flash-high bandwidth memory-graphics processing unit (HBF–HBM–GPU) architecture integrated on a glass interposer for efficient layer-wise weight streaming in transformer-based AI models. To support HBF’s high-bandwidth signaling—comparable to HBM3—required for ultra-scale AI inference, we design a 6 Gbps interconnection channel with 1024 I/O pins, achieving a throughput of 768 GB/s and supporting up to 512 GB capacity per HBF stack.

ABSTRACT. The 2011 earthquake inflicted structural damages that triggered the failure of critical systems at the Fukushima Daiichi nuclear power plant. Today, the main goal is to decommission the still-highly irradiated areas ($ \sim $ 1,000 Sv/h). VLSIs (Very Large Scale Integration) are sensitive to radiation but suitable for this use with proper architecture due to its remapping capability. State-of-the-art space-grade computing platforms, based on CPUs or custom VLSIs, are only capable of supporting a mission lifetime of 10 hours. Early evaluations of the developed radiation-hardened optoelectronic FPGA (ORGA) indicate that it can sustain operation for up to 417 days in such environments, making it possible to initiate decommissioning work. The configuration capability of the ORGA relies on compact and robust light point generation. This paper presents the first steps toward an industrial-grade, scalable solution.

ABSTRACT. Organic interposers for chiplet applications are gaining interest due to the potentially lower cost involved. However, the adhesion of the metal-dielectric layer in an organic interposer has been a challenge in conventional photolithography processes. To address this issue, a mesh plane is considered from a design approach. At the same time, it is of interest to the designer to optimize the electrical performance for chiplet applications. In this paper, the design and signal integrity simulation of interconnects based on an organic interposer with mesh planes is presented. The results are compared to those of solid planes, where the

ABSTRACT. Polynomial chaos expansion suffers from the curse of dimensionality in high-dimensional uncertainty quantification. This paper presents a novel Riemannian tensor train completion method to address the curse of dimensionality. The method incorporates rank-1 initialization and quadrature-weighted sampling to enhance convergence. Validation on a transmission line network with 29 random parameters demonstrates superior accuracy and reduced computational cost compared to existing polynomial chaos methods.

ABSTRACT. This paper compares the eye patterns of received signals in cables of 1 m, 2 m, 4 m, and 10 m lengths using STQ (shielded twisted quad) cables, which are four parallel transmission lines with different lengths of shielding, in order to evaluate the crosstalk suppression effect between channels in mode-division multiplexed transmission systems. The authors have proposed a mode-division multiplexed transmission system that can transmit four-channel signals in parallel using this STQ cable. As a result, no deterioration was observed in the size of the eye opening. In addition, it was confirmed that relatively stable transmission characteristics were maintained despite changes in cable length.

ABSTRACT. We investigate the suppression effect achieved by implementing a lossy resonator filter tuned to a resonant frequency of 2.45 GHz, which corresponds to the center frequency of the 2.4 GHz band used for Wi-fi communication. When we compared the suppression amount values obtained by the estimation formula based on the equivalent circuit model and full-wave analysis, the discrepancy was less than approximately 2 dB, and indicates relatively high accuracy due to the absence of higher-order resonances. Therefore, it was found that even when the resonant frequency of the lossy resonator filter does not match the anti-resonant frequency of the power bus, the suppression amount can still be estimated within approximately 2 dB. This is useful for deriving a bandwidth estimation formula for the suppression characteristics of the lossy resonator filter.

ABSTRACT. We have developed various package substrates primarily composed of glass material, including RDL interposer, glass interposer and glass core substrate. Furthermore, we have presented the results of these developments at several academic conferences. It is important to clarify the transmission performance and its reliability of the fine wiring, which is a common element in these structures. In this paper, we report on the changes observed in the transmission wiring through long-term reliability test. We employed a temperature cycling test for this evaluation. We subjected them to the temperature range of 150 degrees Celsius to -55 degrees Celsius in accordance with JEDEC class H standards. Insertion loss characteristics were measured for each cycle using a network analyzer. We summarize the key features of our fine wiring structure based on the result of this evaluation.

ABSTRACT. Abstract—In this work, we demonstrate a 3D-SiP Power IC packaging approach that achieves a 20% reduction in x-y footprint while maintaining electrical performance. The vertical stacking of components allows for greater power density and compact system integration, making it suitable for next-generation power modules. Electrical measurements confirm no degradation in efficiency, indicating that the miniaturization does not compromise functional performance. However, thermal challenges emerge due to increased power density and limited heat dissipation paths. To address this, comprehensive thermal simulations were conducted to analyze heat accumulation and identify critical hot spots. Optimized thermal management solutions were implemented, including enhanced heat spreading layers and improved thermal vias. These improvements reduced the junction-to-board thermal resistance (ΨJB) from 31.62°C/W to 23.35 °C/W, effectively mitigating thermal impact and ensuring reliable operation. The proposed solution highlights the trade-offs and benefits of vertical integration in power ICs and provides a guideline for future compact power system designs.

ABSTRACT. Transient temperature distribution in the multilayered packaging is usually analyzed by the computational fluid dynamics with an intensive time-step in Ansys Icepak to ensure its accuracy yet with a significant computational cost. Without an explicit time-stepping constraint, the frequency domain vector fitting method to evaluate the transient thermal response is thus proposed to enable an efficient reconstruction of its time-domain behavior in a good agreement with Icepak’s.

ABSTRACT. The growing demand for high-performance computing driven by AI advancements necessitates larger package substrates for highly integrated and dense semiconductor packaging. However, larger substrates increase package warpage after chip mounting due to the coefficient of thermal expansion (CTE) mismatch between the substrate and the silicon chip. Therefore, low-CTE core materials, such as organic resins, glass cloths, and glass cores, have been investigated to mitigate the issue. Despite their advantages, the significant reduction of the CTE of core materials has led to a new challenge. Substrate warpage prior to chip mounting arises due to CTE mismatches between core materials and other substrate components, such as build-up films and copper. Addressing both package and substrate warpage is crucial not only for maintaining structural stability but also for preventing contact failures, signal distortion, and reduced device reliability. In this paper, we propose a new organic core design featuring asymmetric lamination of two types of prepregs with differing thermo-mechanical properties to address both package and substrate warpage. By performing the Finite Element Method (FEM) simulations, we reveal that the substrate warpage can be significantly reduced by employing asymmetric organic cores when the CTE of one prepreg is lower than that of the other. Furthermore, such asymmetric organic cores also contribute to reducing the CTE mismatch between the substrate and the silicon chip. Therefore, these asymmetric organic cores could potentially serve as a solution to address both types of warpage.

ABSTRACT. This paper presents a novel interpretation of near-end crosstalk (NEXT) and far-end crosstalk (FEXT) as sources of signal distortion and proposes a passive amplifier model leveraging the reflections of NEXT and FEXT. The proposed model employs a broadside coupling structure designed for high-speed signals on printed circuit boards (PCBs), intentionally inducing crosstalk within the same signal lines rather than between distinct signals, and harnesses the resulting reflected waves for signal amplification. This paper theoretically analyzes the characteristics of crosstalk, influenced by variations in mutual inductance and capacitance, within a broadside coupling structure. Based on this analysis, a signal enhancement model is proposed to improve system performance. The proposed passive amplifier approach is expected to significantly enhance signal integrity in high speed circuits.

ABSTRACT. In the product development of high-speed, high-frequency printed circuit boards, EMC design at the development stage is more important than EMC measures after the product is completed. A lot of EMC design rules are required for good EMC design. In addition, the use of electromagnetic field analysis simulators is indispensable in order to research and verify design rules. Recently, with the evolution of AI, methods such as simulation efficiency and surrogate models have been devised. In the field of electromagnetic field analysis, research on the use of AI in the fields of SI and PI has become popular. However, EMC-related AI applications are not yet very popular. One of the reasons for this is that there are many feature patterns of electromagnetic fields output from many design parameters, and there are few feature patterns that are problematic compared to feature patterns that are not problematic. In this study, we classify the electric near-field distributions of the power supply ground plane of the printed circuit board by AI clustering and confirm the classification results of problematic feature patterns. We improved the learning method and confirmed that the results of training and testing by AI machine learning are good. In addition, as a new attempt, we confirmed that machine learning can classify the feature pattern of the problematic electric field distribution with a high accuracy rate by increasing the number of data on the electric field distribution near the frequency in problematic and setting the data.

ABSTRACT. In this paper, we first propose a statistical eye-diagram estimation method for pulse amplitude modulation-4 (PAM-4) based high-speed channel considering crosstalk. To consider statistical crosstalk effects, the 3-level transition crosstalk responses are regarded as inputs when statistically estimating each transition level. Statistical eye-diagrams are derived based on recursive convolution between the probability density functions (PDFs) of output pulse responses and crosstalk responses affecting each other. The proposed method provides not only the eye-diagram considering crosstalk noise but also a bit-error rate (BER) analysis. The proposed method is verified by comparing the estimated PAM-4 statistical eye-diagrams with eye-diagrams obtained using a full transient simulation. Comparison of the eye-width and eye-height of the eye-diagrams shows a good correlation between the simulated and the proposed method.

ABSTRACT. Organic substrates are the main carriers for achieving 2D-chiplet integration but they have difficulty supporting 32 Gbps data rate specified by the UCIe-S protocol and have a serious mechanical mismatch with silicon. Glass substrates are considered to be the next-generation substrates for chiplet integration. However, the number of metal layers used for routing is strictly limited by the manufacturing process, which makes crosstalk control a huge challenge. This paper studies the signal integrity of microstrip routing on glass substrate using only two metal layers. We propose possible routing strategies and study the influence of substrate materials. Finally we show a 2D glass substrate layout design that achieves 32 Gbps data rate and meets the requirement of the UCIe 2.0 Standard Package x16 protocol.

ABSTRACT. Adaptive frequency sampling (AFS) aims to reduce the number of computationally expensive electromagnetic (EM) simulations required for the accurate characterization of high-frequency components. This paper introduces a novel uncertainty-guided AFS scheme that employs a rational mixture kernel within a Gaussian Process (GP) model to capture frequency-dependent correlation structures in microwave S-parameters. By leveraging the probabilistic nature of GPs, a cross-validation-based acquisition strategy is introduced to adaptively sample uncertain regions exhibiting high local variation. Integrated within the kernel-aided rational macromodeling (KARMA) framework, the proposed approach enables the construction of compact rational state-space models with enhanced accuracy and reduced simulation cost.

ABSTRACT. Silver is a widely utilized metal in printed electronics for heaters and electrodes due to its excellent electrical conductivity and chemical stability. However, most studies are dependent on commercially available nano-silver inks, which are expensive and hence limit the large-scale experimentation and production of devices. In this work, we have developed a low-cost method for nanoparticle synthesis and electrode fabrication for sensing applications. We optimized the synthesis to develop Ag nanoink which exhibits a viscosity of 0.005 Pa.s, making it compatible for inkjet printing using a standard desktop printer. A prototype of interdigitated electrodes (IDE) is fabricated by depositing ten successive layers of the silver ink on photo paper substrate. We demonstrate a low-cost electrode fabrication using inkjet printing that has higher conductivity and lower sheet resistance compared to earlier studies. These printed electrodes have great potential for application in flexible electronic devices, including low-cost gas sensors

ABSTRACT. We present a specialized measurement setup for active topside probing of D-band antenna arrays, designed to eliminate probe interference by placing the probe landing pad on the backside of the carrier, opposite the radiating aperture. This setup enables wireless data transmission measurements with an integrated active D-band antenna array comprising a SiGe power amplifier (PA) wirebonded to a PCBintegrated 4×1 subarray. Using this setup, we demonstrate a maximum symbol rate of 22.5 Gbaud and achieve a peak data rate of 100 Gbit/s with a 20 Gbaud 32-QAM signal while maintaining an error vector magnitude (EVM) of 19% at a measurement distance of 25 cm.

ABSTRACT. In this study, a GaN-HEMT die was pressure-bonded to Graphite carbon for heat dissipation without using brazing or adhesive materials. A GaN-die with Au plating on the backside can be pressure bonded to a Graphite carbon with Au electroplating. The GaN-die surface temperature during transistor operation was measured, and it was found that the pressure bonding process generates less temperature-rise than the adhesive bonding process using conventional AuSn brazing technique. Since a die with a hollow backside could be pressure bonded to Graphite carbon, pressure bonding is expected to be a means of package-independent bonding.

ABSTRACT. We have previously proposed an IDDQ test method and its test circuit to detect open defects occurring at interconnects between dies in 3D stacked ICs. The test circuit consists of an I-V converter and a switched-capacitor comparator that uses a self-biased inverter gate. We examined the detectability of resistive open defects at a specific test temperature in our previous work. Since the detectability may depend on the test temperature, we examined it using Spice simulations. The simulation results confirmed that the minimum detectable resistance of open defects is dependent on the test temperature, with lower temperatures enabling the detection of smaller resistance defects.

ABSTRACT. This study focuses on analyzing and evaluating the signal integrity of the two types transmission lines for inter-chip interconnect on Silicon-Interposers used for 2.5D packaging, through simulation. To investigate how changing the L/S (line/space) ratio affects signal integrity without changing the cross-sectional area of the signal line, three different wiring pattern models were simulated. The results show that the Stripline structure achieves up to approximately 4 dB reduction in insertion loss compared to the grounded coplanar waveguide (GCPW) structure. Additionally, crosstalk was observed to be reduced by as much as 5 dB. Furthermore, increasing the height of the signal line effectively mitigates crosstalk in both structures; however, this geometric modification also leads to an increase in insertion loss. These findings provide valuable insights for optimizing interconnect design in advanced packaging technologies.

ABSTRACT. In this paper, for the partial component equivalent circuit (S-PEEC) model with non-uniform dielectric circuits, the corresponding full-wave microcircuit model (MMC) is proposed, and the low-order equivalent circuit of S-PEEC is established. This method obtains a concise circuit model by iteratively using equivalent circuit absorption nodes. The proposed method retains the physical meaning of circuit components without involving any matrix inversion or decomposition. Moreover, its computational overhead is mainly composed of the outer product of vectors, making it highly suitable for GPU acceleration to enhance the simulation efficiency of large-scale high-speed/microwave circuits. A numerical example is given in the text to demonstrate the accuracy and efficiency of this method.