Design and Implementation of an 8-Bit Data Comparator Using Multiplexer Logic for Low Power and Area Optimization

EasyChair Preprint 12321

Abstract

A new innovative approach is presented for an efficient and low-power data comparator using multiplexer logic. The proposed method involves the use of a multiplexer-based configuration of the borrow equation within a full subtractor, serving as a fundamental processing element of the data comparator. This model was executed using the Cadence tools and implemented in Verilog for simulation, enhancing its practicality and applicability across different technologies. By integrating a modified borrow equation into the full subtractor design using multiplexers, a decrease in the number of transistors was achieved, resulting in reduced power consumption. Furthermore, a comparative analysis across various technologies revealed substantial reductions in power usage and physical space requirements when transitioning from 180nm to 90nm and 45nm technologies. These findings highlight the potential for considerable power and area savings in practical image processing applications through this innovative approach.

Keyphrases: 2:1 Multiplexer, Data Comparator, Full Subtractor, Half Subtractor, Power and Area Efficiency

@booklet{EasyChair:12321,
  author    = {Madugula Sumalatha and M.V Ganeshwara Rao and Pattapu Aruna Kumari and Odugu Swathi Siddeswari and Mallidi Lakshmi Kalyani Rekha and Muttha Priyanka},
  title     = {Design and Implementation of an 8-Bit Data Comparator Using Multiplexer Logic for Low Power and Area Optimization},
  howpublished = {EasyChair Preprint 12321},
  year      = {EasyChair, 2024}}