Conference: FMCAD 2018 (Formal Methods in Computer Aided Design 2018)

Conference: FMCAD 2018 (Formal Methods in Computer Aided Design 2018)

This page shows all presentations from this conference published in EasyChair Smart Slide.

Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms

Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms

Thomas Pani, Georg Weissenbacher and Florian Zuleger

Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation

Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation

Bjørnar Luteberget, Koen Claessen and Christian Johansen

k-FAIR = k-LIVENESS + FAIR: Revisiting SAT-based Liveness Algorithms

k-FAIR = k-LIVENESS + FAIR: Revisiting SAT-based Liveness Algorithms

Alexander Ivrii, Ziv Nevo and Jason Baumgartner

Temporal Prophecy for Proving Temporal Properties of Infinite-State Systems

Temporal Prophecy for Proving Temporal Properties of Infinite-State Systems

Oded Padon, Jochen Hoenicke, Kenneth L. McMillan, Andreas Podelski, Mooly Sagiv and Sharon Shoham

Deductive Verification of Distributed Protocols in First-Order Logic

Deductive Verification of Distributed Protocols in First-Order Logic

Certifying Proofs for LTL Model Checking

Certifying Proofs for LTL Model Checking

Alberto Griggio, Marco Roveri and Stefano Tonetta

Template-Based Verification of Heap-Manipulating Programs

Template-Based Verification of Heap-Manipulating Programs

Viktor Malík, Martin Hruska, Peter Schrammel and Tomas Vojnar

Prioritizing Lemmas While Pushing

Prioritizing Lemmas While Pushing

Hari Govind Vediramana Krishnan

Bit-Vector Interpolation and Quantifier Elimination by Lazy Reduction

Bit-Vector Interpolation and Quantifier Elimination by Lazy Reduction

Peter Backeman, Philipp Rümmer and Aleksandar Zeljić

Formal Verification of Deep Neural Networks

Formal Verification of Deep Neural Networks

Nina Narodytska

CoSA: Integrated Verification for Agile Hardware Design

CoSA: Integrated Verification for Agile Hardware Design

Cristian Mattarei, Makai Mann, Clark Barrett, Ross Daly, Dillon Huff and Pat Hanrahan

Formal Verification of Unsatisfiability Results

Formal Verification of Unsatisfiability Results

Learning Linear Temporal Properties

Learning Linear Temporal Properties

Ivan Gavran and Daniel Neider

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstraction for Heterogeneous System-on-Chip Verification

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstraction for Heterogeneous System-on-Chip Verification

Hongce Zhang, Caroline Trippel, Yatin Manerkar, Aarti Gupta, Margaret Martonosi and Sharad Malik

Presentations in this collection: 14