ABSTRACT. This work presents a hardware-aware Neural Architecture Search (NAS) framework for video-based human action recognition, targeting real-time deployment on FPGA-based System-on-Chip (SoC) platforms. The proposed method explores a constrained search space of Convolutional Neural Network (CNN)–Recurrent Neural Network (RNN) architectures aligned with a hardware-software pipeline where CNNs are mapped to FPGA Deep Learning Processing Units (DPUs) and RNNs to embedded ARM cores. A reinforcement learning (RL)-based controller, guided by a position-based discounted reward strategy, progressively learns to generate architectures that emphasize high-impact design decisions. Experiments on the UCF101 dataset demonstrate that the proposed architectures achieve 81.07% accuracy, among the highest reported for CNN-RNN models relying exclusively on spatial information. The results validate the effectiveness of the proposed framework in driving hardware-compatible and performance-optimized architecture exploration.

ABSTRACT. Neurosurgery has increasingly embraced advanced imaging and AI to improve surgical precision, particularly in complex procedures such as brain tumor resection, where multimodal imaging guides intervention. Accurate depth estimation is critical when facial morphology is used to register these diverse image modalities. This work presents a depth estimation system that integrates the Intel D405 stereo camera with a modified HITNet architecture, enhanced by a face attention mechanism to improve facial reconstruction. On synthetic data (MetaHuman), the method reduces mean absolute error from 2.29 mm to 2.02 mm; on real multi-camera data (D405 and ZED 2i), it lowers error from 16.91 mm to 14.39 mm, and to 13.85 mm using the weights from the synthetic training. These results highlight the value of domain-specific models and synthetic data for accurate facial depth capture in neurosurgical imaging workflows.

ABSTRACT. This paper presents a system for automatic classification of telecommunication signals using signal processing, multi-domain features fusion, and machine learning techniques. Our system achieves a 97.72% classification accuracy across a wide range of SNR values (-20 dB to 18 dB) using an over-the-air radio-frequency (RF) signals dataset, while maintaining a relatively low complexity (167k learnable parameters). We employ a comprehensive feature extraction methodology that combines time-frequency representations, wavelet transform coefficients, and frequency domain statistics which are processed through a multi-layer architecture. This work demonstrates a systematic approach to signal classification that balances accuracy, computational efficiency, and generalization capability, with potential applications in spectrum monitoring, electronic defense, and cognitive radio systems.

ABSTRACT. This work presents a method for monitoring the radiofrequency output signal of Spin-Hall and Spin-Torque nano-oscillators, aimed at reducing the required electronic circuitry used nowadays. Compared to current implementations, the proposed approach enables a more compact circuit design, lowers power consumption, and enhances overall system performance, facilitating its on-chip integration into practical nanoscale applications.

ABSTRACT. There are many different techniques that can be used to measure small electronic currents. However, if the current exhibits rapid variations in the form of ultra-narrow pulses, no instrument is fast enough to measure it. This is the case with the power consumption of an array of flip-flops undergoing characterization. In this paper, we propose an effective and simple method to measure this type of current pattern: using a capacitor as a power source and obtaining power from its discharge curves. We have validated the obtained power results with post-layout simulations. We used the proposed method with a design manufactured using 65-nm technology. The experimental results demonstrate that the proposed instrument can easily provide all the necessary characterization data for the flip-flop.

ABSTRACT. This work presents a sub-nanowatt Wake-Up Timer for energy-harvesting IoT applications, based on a thyristor-based ring oscillator and asynchronous digital logic. Fabricated in 180 nm CMOS, the circuit has a power consumption of (100 ± 55) pW at 1.2 V with a oscillation frequency of (0.40 ± 0.07) Hz. It includes a programmable prescaler and a 19-bit counter, enabling long sampling intervals with minimal area (compared to other solutions such as Wake-Up Receivers). The design demonstrates stable operation across multiple samples and extended testing, offering a compact and energy-efficient solution for ultra-low duty cycle sensing nodes.

ABSTRACT. In this paper, a 4×4 K-best algorithm of spatial modulation (SM) MIMO detection is presented for visible light communication (VLC) systems. The SM-MIMO detection is composed of a K-best algorithm, an antenna index detection and a channel matrix estimation. The system simulations show that the K-best algorithm reaches near-optimal BER performance with lower computational complexity. Considering the coded bit error rate (BER) of 10^−4 with QPSK modulation scheme, the proposed K-best algorithm can achieve the maximum SNR loss of 1 dB compared with maximum likelihood (ML) detection.

ABSTRACT. Many modern applications—from logistics to machine learning—demand rapid solutions to complex optimization tasks such as Maximum-Cut (Max-Cut) problems, which involves dividing a graph’s vertices into two disjoint sets to maximize the number of edges between them. Tackling very large graphs often relies on partitioning the problem into moderate-sized subgraphs, which can then be processed efficiently using hardware accelerators. In this study, we present a digital Ising-based solver implemented on reconfigurable hardware, comparing a Hopfield-network update scheme with a Tabu Search algorithm. Obtained results indicate that Tabu Search not only converges more reliably than the Hopfield approach but also outperforms a CPU-based, quantum-inspired implementation in terms of solution quality and speed.

ABSTRACT. This work presents a comparative study of the Full Adders designed using DTMOS Schmitt-Trigger (DST) standard cells in 130 nm SOI CMOS technology, targeting ultra-low supply voltages below 100 mV. Extensive post-layout Monte Carlo simulations were performed to evaluate robustness. The performance of the Full Adders was analyzed in terms of energy, delay, power and energy delay product across a range of supply voltages. The results show that the NAND-only Full Adder (FA) outperforms others, exhibiting the highest yield, lowest delay, smallest area and superior energy efficiency. Additionally, a comparison with the Schmitt-Trigger (ST) NAND-only FA demonstrates that DST FA offer greater robustness and improved energy efficiency. The minimum energy point (MEP) of the DST-based FA ring oscillator is 140 mV compared to the 170 mV MEP of its ST counterpart.

ABSTRACT. The ongoing evolution of wireless communication systems has driven the need for higher operating frequencies, resulting in increased complexity in circuit design, particularly in radio frequency integrated circuits (RFICs). Among the critical components in these systems are on-chip transformers, whose design poses significant challenges due to the intricate electromagnetic behavior at high frequencies. Traditional design methodologies rely heavily on iterative electromagnetic (EM) simulations, which are computationally expensive and time-consuming, often dominating the overall design cycle. To address this, a Machine Learning-based application was developed using radial basis function neural networks (RBFNN), allowing users to input desired transformer characteristics and receive a corresponding physical design. The tool was trained with data from automatically generated and simulated transformers, and includes an optimizer to tailor designs to user specifications. Its effectiveness was validated by redesigning a published circuit and comparing the results with the original.

ABSTRACT. This paper presents a comprehensive theoretical expression for Current Efficiency (CE) in Charge Pump (CP) circuits, incorporating the effects of parasitic capacitances of stage capacitor and Charge Transfer Switch (CTS), current consumption of clock buffer circuit, and a design optimization method for buffer and CTS sizing to maximize CP efficiency. The theoretical findings are validated through simulation of a 5-stage CP, employing a cross coupled CP architecture with gate boosting technique, demonstrating a close match between simulated and theoretical results with a negligible error of 1%.

ABSTRACT. This paper presents a power management integrated circuit (PMIC) designed for battery less energy harvesting (EH) applications. The design features a low-quiescent-current energy management (EM) circuit and a modified CMOS passive rectifier. Post-layout simulations in 65 nm CMOS show that the EM consumes less than 35 nA at a 2.7 V supply, and the total conversion efficiency of the PMIC is 77%. The design is well-suited for applications with extremely energy-limited AC sources, operating with input currents as low as 200 nA and input voltages above 2.7 V.

ABSTRACT. A capacitor-less low-dropout (LDO) regulator with nanosecond-transient response for modern smart edge AI processors is presented. The LDO employs an operational transconductance amplifier (OTA) as the error amplifier and an inverter-based amplifier that provides a high DC gain. The proposed LDO was designed in 65-nm complementary metal oxide semiconductor (CMOS), allowing for an output range of 0.4-1.6 V from an 1.8 V input and a maximum 300 mA load current. The simulated output undershoot is 60 mV with a load current step from 10 to 300 mA and a 20 ns edge-time. The proposed LDO consumes 243 µA and has a transient response time of 9.97 ns with steps of 10 to 300 mA and 37.2 ns with steps of 300 to 10 mA.