VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION

This page contains an index consisting of author-provided keywords.

1
130nm CMOS	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
5
5G LNA	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
6
6G	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
A
ADC	Extended Abstract: FPGA Digitization of Radar Signals
Advanced Encryption Standard (AES-128)	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
AI	AI-Assisted Digital Implementation Design Flow using Cadence Cerebrus Intelligent Chip Explorer
AI Acceleration	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
AI processor	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
antenna-on-chip	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
APB	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Application-specific ISA	Integrated Dynamic Memory Manager for a RISC-V Processor
Approximate Computing	Method for Data-Driven Pruning in Micropipeline Circuits Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application
Approximate Divider	Design of Power Efficient Approximate Square Root for Ultrasound imaging system Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application
Approximate Multiplier	Power Efficient Approximate Multiplier for Neural Network Applications
Arbiters	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification
artificial magnetic conducto	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
Artificial neural networks	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
ASIC acceleration	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Asynchronous	Method for Data-Driven Pruning in Micropipeline Circuits
asynchronous-logic masked AES accelerator	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Autism	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
AXI	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
B
backdoors	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Backplane interconnect	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Barrett Reduction	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Bi-Directional Amplifier	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
Bias	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
bias detection	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Biomaterials	Tutorial: Biomaterials and their application in flexible electronic devices: fabrication and characterization
Bond wire based Inductor	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Breathing Rate	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
Buck Converter	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Bufferless router	Fine Tuning Network Performance in Bufferless On-chip Networks
Bundled-Data	Method for Data-Driven Pruning in Micropipeline Circuits
C
Call Option Payoff Function	Optimized Quantum Circuit Implementation of Payoff Function
Carry-lookahead Adder	Reducing Depth of Quantum Adder using Ling Structure
Channel-first dataflow	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
characterization	Tutorial: Biomaterials and their application in flexible electronic devices: fabrication and characterization
Chip Certification	Zero-Trust Communication between Chips
Chip-to-chip communication	Zero-Trust Communication between Chips
ChipWhisperer-Lite	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
CIM	Mapping of CNNs on multi-core RRAM-based CIM architectures
CKKS	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
CMOS LNA	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
CMOS quantum computing	Noise modeling using look-up tables and DC measurements for cryogenic applications
CMOS rectifier	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
CNN	Mapping of CNNs on multi-core RRAM-based CIM architectures
CNN accelerator	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Cold source	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
comparative analysis	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Compute-in-memory	Memory-based computing for energy-efficient AI: Grand challenges
Compute-In-Place	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Computer Architecture	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Confidential inference	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
confidentiality	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Connected component algorithm	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
continues development	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
continues integration	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Continuous Conduction Mode	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Control	Tutorial: Industrial Control Systems Security
convolution	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
Convolutional Neural Network	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
Correlation Power Analysis (CPA)	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Correlation Power Attack	Correlation Power Attacks on TEA
CPU	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Critical Embedded Systems	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
cryogenic modeling	Noise modeling using look-up tables and DC measurements for cryogenic applications
Cryptography	Correlation Power Attacks on TEA
CUDA	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Cyclic Logic Encryption	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
D
DAC	Extended Abstract: FPGA Digitization of Radar Signals
Data-Driven Pruning	Method for Data-Driven Pruning in Micropipeline Circuits
dataflow analysis	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
datasets	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
DC-DC Power Converter	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Decision trees	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
deep learning	Memory-based computing for energy-efficient AI: Grand challenges
Deflection rate	Fine Tuning Network Performance in Bufferless On-chip Networks
delta–sigma modulator (DSM)	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Depthwise separable convolution	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
design optimization	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
design space exploration	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Detection	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion Real-Time Switched Capacitor Based Power Side-Channel Attack Detection
Differential Power Analysis (DPA)	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Digital demodulation	Extended Abstract: FPGA Digitization of Radar Signals
Digital Implementation Design Flow	AI-Assisted Digital Implementation Design Flow using Cadence Cerebrus Intelligent Chip Explorer
Digital radar	Extended Abstract: FPGA Digitization of Radar Signals
Dynamic memory manager hardware	Integrated Dynamic Memory Manager for a RISC-V Processor
Dynamic Partial Reconfiguration	Hardware Security against Replay Attacks at Partial Reconfiguration
E
EDA	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Edge AI	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
Edge computing	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
edge oxidation	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
eDRAM	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Embedded instrument	On Protecting IJTAG using an Inherently Secure SIB
Embedded systems	Dynamic Scheduling for Event-Driven Embedded Industrial Applications Hardware Implementation and Evaluation of an Information Processing Factory
Emerging Technology	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
energy-efficiency	Memory-based computing for energy-efficient AI: Grand challenges
Envelop detection	Design of Power Efficient Approximate Square Root for Ultrasound imaging system
Error-resistant architectures	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Event-Based	Method for Data-Driven Pruning in Micropipeline Circuits
Event-Driven Tasks	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
F
fabrication	Tutorial: Biomaterials and their application in flexible electronic devices: fabrication and characterization
failure	Hardware Implementation and Evaluation of an Information Processing Factory
Fano factor	Noise modeling using look-up tables and DC measurements for cryogenic applications
fault detection	Hardware Implementation and Evaluation of an Information Processing Factory
Fault Injection	Formal Evaluation of Digital Circuits Robustness
FeFET Design	FeFET based Logic-in-Memory design methodologies, tools and open challenges
FeRAM	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
FHE	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Field Programmable Gate Arrays	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
FinFET	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Flash ADC	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
flexible electronic devices	Tutorial: Biomaterials and their application in flexible electronic devices: fabrication and characterization
Floating-point numbers	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Formal Methods	Formal Evaluation of Digital Circuits Robustness
Formal Verification	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification Zero-Trust Communication between Chips Formal Evaluation of Digital Circuits Robustness
FPGA	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation FPGA-implementation techniques to efficiently test application readiness of mixed-signal products Extended Abstract: FPGA Digitization of Radar Signals Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
FPGA routing	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
FPGA Security	Hardware Security against Replay Attacks at Partial Reconfiguration
fractional-N frequency synthesizer	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Fully Homomorphic Encryption	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
G
Gate compounding	Synthesis of SFQ Circuits with Compound Gates
genomics	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Gigabit Radio	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
GPU	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Graph Neural Network	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Graphics Processing Units (GPUs)	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
H
hardware accelerator	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
hardware emulation	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
Hardware Security	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Hardware Trojan	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Heart Rate	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
High Throughput	Method for Data-Driven Pruning in Micropipeline Circuits
Human Emotions	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
Hybrid memory	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Hyperdimnesional Computing	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
I
IEEE Std. 1687	On Protecting IJTAG using an Inherently Secure SIB
Image processing	Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application
in-memory computing	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing Resistive RAM for computing: How reliable ?
In-package wireless communication	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Industrial	Tutorial: Industrial Control Systems Security
Industrial Applications	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
information flow analysis	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Information Processing Factory	Hardware Implementation and Evaluation of an Information Processing Factory
Integrated Circuits	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
Intelligent Chip Explorer	AI-Assisted Digital Implementation Design Flow using Cadence Cerebrus Intelligent Chip Explorer
interoperable PDK	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
IoT Applications	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
irradiation test	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
ISSIB	On Protecting IJTAG using an Inherently Secure SIB
K
K-means algorithm	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
L
large kernel	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
large language models	Memory-based computing for energy-efficient AI: Grand challenges
Last Level Cache	Improving Lifetime and Performance of Non Volatile Memory Caches
Latency	Fine Tuning Network Performance in Bufferless On-chip Networks
LDO	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
LFMCW RADAR	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
LFSR	On Protecting IJTAG using an Inherently Secure SIB
Ling Adder	Reducing Depth of Quantum Adder using Ling Structure
LNA	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
Load balancing	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Logic Feedback Loop	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Logic Locking	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Logic synthesis	Synthesis of SFQ Circuits with Compound Gates
look-up table design	Noise modeling using look-up tables and DC measurements for cryogenic applications
Low Power	Method for Data-Driven Pruning in Micropipeline Circuits Design of Power Efficient Approximate Square Root for Ultrasound imaging system Power Efficient Approximate Multiplier for Neural Network Applications
Low-power design	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Low-power memory	Memristor-Based Power Efficient SRAM Cell
LSSP	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
M
Magnetic Tunnel Junction	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
maximum sequence length	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
memory access	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
memory diagnosis	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
memory feature extraction	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Memristor	Memristor-Based Power Efficient SRAM Cell
mixed-signal emulation	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
mm-Waves	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Modular Multiplier	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Morphology	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Multi-chiplet systems	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
multistage noise shaping (MASH)	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Méthodologie	FeFET based Logic-in-Memory design methodologies, tools and open challenges
N
Near-memory computing	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
Negative Emotions Outburst	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
Network-on-Chip	Fine Tuning Network Performance in Bufferless On-chip Networks
neural network	Resistive RAM for computing: How reliable ?
neural networks	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
noise estimation	Noise modeling using look-up tables and DC measurements for cryogenic applications
Non Volatile Memory	Improving Lifetime and Performance of Non Volatile Memory Caches
non-equilibrium Green’s function (NEGF)	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
NTT Acceleration	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Number theoretic transform (NTT)	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
O
On-chip PVT compensation	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
Order-preserving cryptography	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
P
Packet processing	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Page migration	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Parallel Computation	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Partial Products	Power Efficient Approximate Multiplier for Neural Network Applications
PathFinder	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Payload	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
PE utilization	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
performance evaluation	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Permanent Faults	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
phosphorene nanoribbons	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
Pixel-first dataflow	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
Posit numbers	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Post-quantum cryptography	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
Post-quantum cryptography (PQC)	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Power analysis	Correlation Power Attacks on TEA Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Power Conversion Efficiency	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
Power Converters	Tutorial: High-Frequency Switching Power Converters for Mixed- Signal SoCs
power Side-Channel Attacks (SCA)	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Power Supplies	Tutorial: High-Frequency Switching Power Converters for Mixed- Signal SoCs
Power Supply Network	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Probabilistic Computing	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
process design kit	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Processor architecture	Integrated Dynamic Memory Manager for a RISC-V Processor
product validation	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
property checking	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Pruning Method	Method for Data-Driven Pruning in Micropipeline Circuits
PUF	PR-PUF: A Reconfigurable Strong RRAM PUF
Q
quality assurance	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Quantum Arithmetic	Reducing Depth of Quantum Adder using Ling Structure
Quantum Circuit	Optimized Quantum Circuit Implementation of Payoff Function
Quantum Computers	Optimized Quantum Circuit Implementation of Payoff Function
Quantum Computing	Reducing Depth of Quantum Adder using Ling Structure
Quantum Finance Arithmetic	Optimized Quantum Circuit Implementation of Payoff Function
R
Range-doppler matrix	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Real number arithmetic	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Reconfigurable rectifier	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
reliability	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration Resistive RAM for computing: How reliable ?
Reliable systems	Hardware Implementation and Evaluation of an Information Processing Factory
Reply attacks	Hardware Security against Replay Attacks at Partial Reconfiguration
Resistive crossbars	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
RF energy harvesting	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
RHBD	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
RISC-V	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
RISC-V processor design	Integrated Dynamic Memory Manager for a RISC-V Processor
Robustness	Formal Evaluation of Digital Circuits Robustness
routing	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
RRAM	Mapping of CNNs on multi-core RRAM-based CIM architectures PR-PUF: A Reconfigurable Strong RRAM PUF Resistive RAM for computing: How reliable ?
RTOS	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Runtime verification	Hardware Implementation and Evaluation of an Information Processing Factory
S
safety-critical systems	Hardware Implementation and Evaluation of an Information Processing Factory
Sampler	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
SC-DCDC Converter	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection
Scheduling	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
SDN	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Secure computing	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
Security	PR-PUF: A Reconfigurable Strong RRAM PUF
self-awareness	Hardware Implementation and Evaluation of an Information Processing Factory
self-healing	Hardware Implementation and Evaluation of an Information Processing Factory
SEMNU	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
SEU	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
SIB	On Protecting IJTAG using an Inherently Secure SIB
Side channel attack	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection Correlation Power Attacks on TEA
Single-Flux Quantum	Synthesis of SFQ Circuits with Compound Gates
SmartNICs	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
SoC	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Soft-error	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
Sparse matrix-vector multiplication	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
SPDM	Zero-Trust Communication between Chips
Spintronics	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
SRAM	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications Memristor-Based Power Efficient SRAM Cell
SRAM PUF	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Static noise margin	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
STTRAM	Improving Lifetime and Performance of Non Volatile Memory Caches
subthreshold swing (SS)	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
Superconductive Electronics	Synthesis of SFQ Circuits with Compound Gates
System On Chip	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions Tutorial: High-Frequency Switching Power Converters for Mixed- Signal SoCs
System-on-Chip	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Systems Security	Tutorial: Industrial Control Systems Security
T
T-depth Optimization	Reducing Depth of Quantum Adder using Ling Structure
Task mapping	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
task migration	Hardware Implementation and Evaluation of an Information Processing Factory
TEA	Correlation Power Attacks on TEA
Technology mapping	Synthesis of SFQ Circuits with Compound Gates
Temperature	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Tensor Core Unit (TCU)	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Thermal management	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Thermal Stability	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
Throughput	Fine Tuning Network Performance in Bufferless On-chip Networks
Time-Domain ADC	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Tool	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Track and Hold	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Trigger	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Two-layer connected component algorithm	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
V
vision transformer	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
Vital Signs Detection	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
VLSI Partitioning	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Voltage Regulator	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection
W
Wearable Biomedical Applications	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
weight mapping	Mapping of CNNs on multi-core RRAM-based CIM architectures
Wideband LNA	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
Winograd transformation	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
Write distribution	Improving Lifetime and Performance of Non Volatile Memory Caches
Write-intensive	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Z
Zero trust	Zero-Trust Communication between Chips

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