VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION

A
Abed, Baraa	Extended Abstract: FPGA Digitization of Radar Signals
Abu Al Haj, Amr	Extended Abstract: FPGA Digitization of Radar Signals
Abu Libdeh, Enas	Correlation Power Attacks on TEA
Agarwal, Abhinav	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Ahlawat, Satyadev	On Protecting IJTAG using an Inherently Secure SIB
Ahmad, Uzair	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Ahmed, Ashfaq	Zero-Trust Communication between Chips
Ahmed, Sagheer	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
Al-Othman, Amani	Tutorial: Biomaterials and their application in flexible electronic devices: fabrication and characterization
Al-Qutayri, Mahmoud	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection Correlation Power Attacks on TEA
Albasha, Lutfi	Extended Abstract: FPGA Digitization of Radar Signals
Alhashmi, Amal	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Alshamsi, Hamdan	Zero-Trust Communication between Chips
Altaf, Muhammad Awais Bin	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
Ambulkar, Jayesh	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
Amer, Walaa	Hardware Implementation and Evaluation of an Information Processing Factory
Amrouch, Hussam	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
Andraud, Martin	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
Anil Kumar, Uppugunduru	Design of Power Efficient Approximate Square Root for Ultrasound imaging system Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application Power Efficient Approximate Multiplier for Neural Network Applications
Ansaloni, Giovanni	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Areibi, Shawki M.	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Arva, Venkat Sai	Power Efficient Approximate Multiplier for Neural Network Applications
Asgari, Bahar	Memory-based computing for energy-efficient AI: Grand challenges
Aslam, Abdul Rehman	Design and Analysis of an On-Chip Processor for Autism Spectrum Disorder Children Assistance Using Their Emotions
Atienza, David	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Ayduman, Can	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Aziza, Hassen	Resistive RAM for computing: How reliable ?
Azmi, Haytham	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification
B
Bairamkulov, Rassul	Synthesis of SFQ Circuits with Compound Gates
Baksi, Anubhab	Optimized Quantum Circuit Implementation of Payoff Function
Balasi, Szabolcs	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Belwafi, Kais	Zero-Trust Communication between Chips
Berlingard, Quentin	Noise modeling using look-up tables and DC measurements for cryogenic applications
Bernardi, Paolo	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Bishnoi, Rajendra	Resistive RAM for computing: How reliable ?
Bolar, Gautham	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Bosbach, Nils	Mapping of CNNs on multi-core RRAM-based CIM architectures
Bosio, Alberto	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Braun, Felix	Hardware Security against Replay Attacks at Partial Reconfiguration
Britton Orozco, Giovani Crasby	Noise modeling using look-up tables and DC measurements for cryogenic applications
C
Cao, Ningyuan	Memory-based computing for energy-efficient AI: Grand challenges
Cao, Yunqi	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Casse, Mickael	Noise modeling using look-up tables and DC measurements for cryogenic applications
Chao, Chun Wei	Integrated Dynamic Memory Manager for a RISC-V Processor
Chapuis, Bastien	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Chattopadhyay, Anupam	Reducing Depth of Quantum Adder using Ling Structure PR-PUF: A Reconfigurable Strong RRAM PUF A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion Optimized Quantum Circuit Implementation of Payoff Function
Chauhan, Yogesh Singh	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
Chen, Hanning	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Chen, Xizi	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
Chen, Yi	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
Chennamsetti, Sai Pranay	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Chou, Shan-Hui	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Cubero, Jose	Mapping of CNNs on multi-core RRAM-based CIM architectures
D
Datsuk, Anton	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Datsuk, Anton	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Daveau, Jean-Marc	Formal Evaluation of Digital Circuits Robustness
De Micheli, Giovanni	Synthesis of SFQ Circuits with Compound Gates
Deb, Suman	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Diware, Sumit	Resistive RAM for computing: How reliable ?
Dormieu, Benjamin	Noise modeling using look-up tables and DC measurements for cryogenic applications
Doumanidis, Constantine	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
E
Ecker, Wolfgang	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
Edward, Nermine	Memristor-Based Power Efficient SRAM Cell
Eggermann, Gregoire	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
El-Araby, Nahla	Memristor-Based Power Efficient SRAM Cell Hardware Security against Replay Attacks at Partial Reconfiguration
El-Kharashi, M. Watheq	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification
Elfadel, Ibrahim	Correlation Power Attacks on TEA Experiments in Power Side Channel Attacks: DPA and CPA on AES-128 Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
Engels, Sylvain	Method for Data-Driven Pruning in Micropipeline Circuits
Ershad Ahmed, Syed	Design of Power Efficient Approximate Square Root for Ultrasound imaging system Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application
F
Fang, Yan	Memory-based computing for energy-efficient AI: Grand challenges
Fayed, Ayman	Tutorial: High-Frequency Switching Power Converters for Mixed- Signal SoCs
Fesquet, Laurent	Method for Data-Driven Pruning in Micropipeline Circuits
Fisher, Clément	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Freye, Florian	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
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Galy, Philippe	Noise modeling using look-up tables and DC measurements for cryogenic applications
Gangotri, Aniket	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Gebregiorgis, Anteneh	Resistive RAM for computing: How reliable ?
Gebremicheal, Mizan	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
Gemmeke, Tobias	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
Giraud, Bastien	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Grenouillet, Laurent	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Grewal, Gary	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Guerrero Balaguera, Juan David	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Gupta, Aishwarya	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Gupta, Saransh	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Gurugopinath, Sanjeev	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
H
Halonen, Kari	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
Hamdioui, Said	Resistive RAM for computing: How reliable ? Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Hamed, Sahar	Memristor-Based Power Efficient SRAM Cell
Herkersdorf, Andreas	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Hong, Sheng-Di	Integrated Dynamic Memory Manager for a RISC-V Processor
Hsiao, Ting-Yun	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Huang, Darong	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Huang, Fengyi	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Huang, Juinn-Dar	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Hussain, Jafar	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Hwang, Seong Oun	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
I
Ibrahim, Hala	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification
Ikeda, Makoto	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Imani, Mohsen	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration Memory-based computing for energy-efficient AI: Grand challenges
Insinga, Giorgio	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
J
James, Rekha K	Fine Tuning Network Performance in Bufferless On-chip Networks
Jamil, Shahid	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
Jang, Kyungbae	Optimized Quantum Circuit Implementation of Payoff Function
Jiang, Jingbo	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
Jose, John	Improving Lifetime and Performance of Non Volatile Memory Caches
Joseph, Jan Moritz	Mapping of CNNs on multi-core RRAM-based CIM architectures
Joshi, Dheemanth	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Jou, Jing-Yang	An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
K
Kalyani, Aditya	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
Kanj, Rouwaida	Hardware Implementation and Evaluation of an Information Processing Factory
Kapoor, Hemangee	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Karami, Rachid	Hardware Implementation and Evaluation of an Information Processing Factory
Karimzadeh, Foroozan	Memory-based computing for energy-efficient AI: Grand challenges
Karn, Rupesh	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
Karri, Ramesh	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Keni Yerriswamy, Karthik	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Khalid, Ayesha	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Khan, Esrat	Experiments in Power Side Channel Attacks: DPA and CPA on AES-128
Khan, Safiullah	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Khan, Safwan	Extended Abstract: FPGA Digitization of Radar Signals
Kilani, Dima	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection
Kim, Hyunjun	Optimized Quantum Circuit Implementation of Payoff Function
Kim, Yeseong	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Klotz, Anton	AI-Assisted Digital Implementation Design Flow using Cadence Cerebrus Intelligent Chip Explorer
Kolahimahmoudi, Nima	A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Konstantinou, Charalambos	Tutorial: Industrial Control Systems Security
Koçer, Emre	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Kumar, Gaurav	On Protecting IJTAG using an Inherently Secure SIB
Kumar, Pardeep	On Protecting IJTAG using an Inherently Secure SIB
Kumar, Shanu	Highly Accurate Adaptive Approximate Divider Architecture For Error Resilient Application
Kumar, Shubham	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
Kunthara, Rose George	Fine Tuning Network Performance in Bufferless On-chip Networks
Kurdahi, Fadi	Hardware Implementation and Evaluation of an Information Processing Factory
Kırbıyık, Selim	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
L
Lanius, Christian	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
Latapie, Hugo	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Lauga-Larroze, Estelle	Noise modeling using look-up tables and DC measurements for cryogenic applications
Lee, Wai Kong	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Lesage, Xavier	Method for Data-Driven Pruning in Micropipeline Circuits
Leupers, Rainer	Mapping of CNNs on multi-core RRAM-based CIM architectures SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Li, Junjie	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Liess, Marco	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Lim, Sejin	Optimized Quantum Circuit Implementation of Payoff Function
Limas Sierra, Robert Alexander	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Lin, Yingyan	Memory-based computing for energy-efficient AI: Grand challenges
Loh, Johnson	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
Longchar, Imlijungla	ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
Lou, Jie	An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
M
Maes, Roel	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Maier, Konrad	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
Maniatakos, Michail	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility Tutorial: Industrial Control Systems Security TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Mansour, Ahmad	Extended Abstract: FPGA Digitization of Radar Signals
Mansour, Somaya	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
Marchand, Cédric	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Masoumian, Shayesteh	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Matrangolo, Paul-Antoine	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Medina Morillas, Rafael	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Mendelson, Avi	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Merchant, Farhad	PR-PUF: A Reconfigurable Strong RRAM PUF SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Merio, Cristiano	Method for Data-Driven Pruning in Micropipeline Circuits
Mert, Ahmet Can	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Mir, Hassan	Extended Abstract: FPGA Digitization of Radar Signals
Mir, Salvador	Noise modeling using look-up tables and DC measurements for cryogenic applications
Miranda, José	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Mohammad, Baker	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection Correlation Power Attacks on TEA
Mondal, Debabrata	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
Morin-Allory, Katell	Method for Data-Driven Pruning in Micropipeline Circuits Formal Evaluation of Digital Circuits Robustness
N
N S, Aswathy	Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
Nabeel, Mohammed	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Naimi, Ali	Method for Data-Driven Pruning in Micropipeline Circuits
Nasr, Mostafa	Extended Abstract: FPGA Digitization of Radar Signals
Nassif, Sani	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
Navarro, David	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Nawaz, Kashif	Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
Nicolas, Alban	FeFET based Logic-in-Memory design methodologies, tools and open challenges
Noel, Jean-Philippe	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Numan, Omar	A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
O
O'Connor, Ian	FeFET based Logic-in-Memory design methodologies, tools and open challenges
O'Neill, Maire	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Ostrovskyy, Philip	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
P
P B, Alisha	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
Panzera, Giuseppe	AI-Assisted Digital Implementation Design Flow using Cadence Cerebrus Intelligent Chip Explorer
Pelke, Rebecca	Mapping of CNNs on multi-core RRAM-based CIM architectures
Peon Quiros, Miguel	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Pittala, Mouli Venkata Prakash	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
Prasad, Yamuna	On Protecting IJTAG using an Inherently Secure SIB
R
R. Genssler, PAUL	Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
Rafferty, Ciara	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Rajendran, Gokulnath	PR-PUF: A Reconfigurable Strong RRAM PUF
Rakka, Mariam	Hardware Implementation and Evaluation of an Information Processing Factory
Ramzan, Rashad	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Rana, Vikas	PR-PUF: A Reconfigurable Strong RRAM PUF
Recoquillay, Arnaud	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Reimann, Lennart M.	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Riaz, Anjum	On Protecting IJTAG using an Inherently Secure SIB
Rios, Marco	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
Roche, Philippe	Formal Evaluation of Digital Circuits Robustness
Rodriguez Condia, Josie Esteban	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Rutsch, Gabriel	FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
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S, Nagaveni	Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 V
Sadredini, Elaheh	Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Safar, Mona	Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification
Saghir, Mazen	Hardware Implementation and Evaluation of an Information Processing Factory
Saif, Hassan	A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Saleh, Hani	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection Correlation Power Attacks on TEA
Sanduleanu, Mihai	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies 3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Sarkar, Esha	TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Savaş, Erkay	Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Schrijen, Geert-Jan	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Seo, Hwajeong	Optimized Quantum Circuit Implementation of Payoff Function
Seo, Minjun	Hardware Implementation and Evaluation of an Information Processing Factory
Serunjogi, Solomon	Tutorial: Vital Signs Monitoring at Sub mm-Waves and IC Design Techniques in Modern CMOS SOI Technologies
Serunjogi, Solomon Micheal	3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Shah, Ambika Prasad	Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications
Shah, Yasir Ali	Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Shakil, Muhammad Jawad	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Shamim, Atif	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
Shoufan, Abdulhadi	Zero-Trust Communication between Chips
Siddiqi, Umair F.	A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Singh, Jawar	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
Singh, Simranjeet	PR-PUF: A Reconfigurable Strong RRAM PUF
Sirohi, Ankit	A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
Sisejkovic, Dominik	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Sivakumar, S	Improving Lifetime and Performance of Non Volatile Memory Caches
Soni, Deepraj	Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
Sonza Reorda, Matteo	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Staudigl, Felix	Mapping of CNNs on multi-core RRAM-based CIM architectures
T
Taji, Hossein	Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Tang, Xusheng	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Taouil, Mottaqiallah	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Tempia Calvino, Alessandro	Synthesis of SFQ Circuits with Compound Gates
Thiagarajan, Ganesan	A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Tsai, Chun-Jen	Integrated Dynamic Memory Manager for a RISC-V Processor
Tsui, Chi-Ying	Accelerating Large Kernel Convolutions with Nested Winograd Transformation
U
Usman, Muhammad	Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
V
Valea, Emanuele	Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems
Vater, Frank	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
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Wang, Dr. Guoping	GPU vs CPU Implementation of the Kernighan-Lin Partitioning Algorithm for Improved Partitioning Results
Wang, Rui	Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Wang, Siyi	Reducing Depth of Quantum Adder using Ling Structure Optimized Quantum Circuit Implementation of Payoff Function
Warrier, Dr. Tripti S	Design of stochastic Magnetic Tunnel Junction with an Optimized Free Layer for Probabilistic Spin Logic
Wieden, Christian	Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance Platform
Wiesner, Jonathan	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Wild, Thomas	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
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Younes, Leen	Real-Time Switched Capacitor Based Power Side-Channel Attack Detection Correlation Power Attacks on TEA
Yu, Yiyang	Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
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Zahoor, Furqan	PR-PUF: A Reconfigurable Strong RRAM PUF
Zambelli, Cristian	Resistive RAM for computing: How reliable ?
Zapater, Marina	REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
Zekry, Abdelhalim	Memristor-Based Power Efficient SRAM Cell
Zhang, Youming	A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Ziyang, Ye	Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis Attacks
Zuccala, Damiano	Formal Evaluation of Digital Circuits Robustness
Zyla, Klajd	FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs

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