ABSTRACT. The Cadence® Cerebrus™ Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cerebrus full flow reinforcement learning technology, engineering team productivity is greatly improved.

ABSTRACT. Continuous monitoring of human vital signs, such as breathing rate (BR) and heart rate (HR), is essential for the early identification and even forecasting of disorders that may have an impact on a patient's wellness. The purpose of the workshop is to introduce different methods for Vital Signs Monitoring with the emphasis of LFMCW Radar techniques and present the challenges of an integrated solution at sub mm-Waves (160GHz). First of all, the design trade-offs at system level will be presented, followed by circuit design like, LNA, PA, PLL (IQ-VCO, Frequency dividers, Charge pump), Mixers. Thereafter, different algorithms for extracting breathing rate and heart rate are discussed

ABSTRACT. The workshop provides a platform for researchers, scientists, and industry professionals to gain additional knowledge, expertise, and recent advancements in the field of biomaterials and their applications in flexible electronics/neural sensing applications. The Participants can learn about different materials, fabrication techniques, characterization methods, and emerging trends.

ABSTRACT. With the increasing demand for a larger number of highly-efficient fully integrated power supplies within Systems-on-Chip (SoC), there is a need for developing switching power regulators with very high switching frequencies (tens or hundreds of MHz) with small enough passive components that can be integrated on-chip or co-packaged with the SoC. However, this involves many challenges, such as large switching losses, higher resistive parasitics and leakage associated with on-chip and on-package passives, and the difficulty of implementing power switches using low-voltage devices in nanometer CMOS. This tutorial will present the various techniques used to implement high-frequency fully-integrated power supplies in mixed-signal SoCs, along with a discussion of the advantages and shortcomings of each technique taking into account factors such as design complexity, silicon area, efficiency, and dynamic performance.

ABSTRACT. Cyberattacks on critical infrastructure can have a debilitating effect on national economic security, public health, and safety. The underlying processes of the various critical infrastructure sectors are controlled by Industrial Control Systems (ICS). ICS are transitioning from legacy, electromechanical-based systems to modern information and communication technology-based systems, creating a close coupling between cyber and physical components. This transition greatly expands the attack surface of such systems, as cyberattacks targeting commercial-off-the-shelf hardware and software are well-known. This tutorial introduces basic and advanced topics on industrial control systems security. It starts with operational security, providing guidance on recognizing weaknesses in everyday operations and information which can be valuable to attackers. A comparative analysis between traditional information technology (IT) and control system architectures is also presented, along with security vulnerabilities and mitigation strategies unique to the control system domain. Current trends, threats, and vulnerabilities will be discussed, as well as attacking and defending methodologies for ICS. Case studies on cyberattacks and defenses will be presented for two critical infrastructure sectors: the power grid and the chemical sector. The tutorial also discusses the need for an accurate assessment environment, achieved through the inclusion of Hardware-In-The-Loop testbeds.