SBAC-PAD 2026: 38TH IEEE/SBC INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD)

This page contains an index consisting of author-provided keywords.

3
3d-stacked memory	Vector-In-Memory Architecture for Data-centric Applications
A
AI accelerator	Implementation and Acceleration of MLP-Based IDS for FPGA
AI Inference	Predicting the Effectiveness of GPU Sharing for AI Inference on Aurora
Allgather	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
AllReduce	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
Alltoall	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
Approximate Computing	FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
architecture-aware optimization	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
Arm SPE	Assessing Arm SPE for Automatic Data Placement in Heterogeneous Memory Systems
artificial intelligence	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems
Automatic Data Distribution	Assessing Arm SPE for Automatic Data Placement in Heterogeneous Memory Systems
B
bandwidth	YABLT: Modeling Memory Bandwidth Effects by Limiting Bandwidth Availability
Benchmarking	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC
BFloat16	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
big data	Vector-In-Memory Architecture for Data-centric Applications
bitstream cache	LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
BLAS	Zero-Copy GEMM-Based Fast Convolution
Branch prediction	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
C
cache	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs New techniques to reduce cache interference in real-time mixed-criticality systems on multicore platforms
cache coherence	Analysis and Implementation Alternatives of Multi-grain Coherence Directories
cache multi-GPU inference MFU	Parallelizing Deep Learning: A Unified Study of CPU and GPU Partitioning Strategies, Bottlenecks, and Design Principles
Cache performance	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
Candidate Reduction	Resource-Aware Model Selection for Scalable Indoor Localization on HPC Platforms
categorization	A Methodology for System-Scale I/O Pattern Taxonomy for HPC Workloads
cloud economics	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
Cloud workload characterization	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
code generation	Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework Cross-Platform MLIR Based GEMM Micro-Kernel Generation
codesign	YABLT: Modeling Memory Bandwidth Effects by Limiting Bandwidth Availability
Collective Operations	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
Compiler infrastructures	Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework
compute marketplace	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
Computer Architecture	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC Analysis and Implementation Alternatives of Multi-grain Coherence Directories
Convolution	Zero-Copy GEMM-Based Fast Convolution
CPU usage prediction	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
Cross-application interference	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
Cross-Layer Analysis	Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
cross-vendor	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
CUDA	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
custom instruction	LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
Cybersecurity	Implementation and Acceleration of MLP-Based IDS for FPGA
D
Data Augmentation	Design and Evaluation of Continuous Synthetic Data Pipelines for Vision Pre-training
Data Pipelines	Design and Evaluation of Continuous Synthetic Data Pipelines for Vision Pre-training
Data prefetching	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
Data synchronization	Phoning Home: Repatriating output from cloud jobs with a user-level, provider-agnostic data transfer tool
DDR5	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
decentralised infrastructure	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
Deep learning	Resource-Aware Model Selection for Scalable Indoor Localization on HPC Platforms Implementation and Acceleration of MLP-Based IDS for FPGA GPU-Efficient XAI Uncertainty Estimation for nnUNet
deep learning parallelism SIMD AVX-512	Parallelizing Deep Learning: A Unified Study of CPU and GPU Partitioning Strategies, Bottlenecks, and Design Principles
Deep Learning Systems	Design and Evaluation of Continuous Synthetic Data Pipelines for Vision Pre-training
Deep neural networks	Implementation and Acceleration of MLP-Based IDS for FPGA
Design Space Exploration	Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
directory compression	Analysis and Implementation Alternatives of Multi-grain Coherence Directories
Distributed Learning	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
DLFloat	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
DNN	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
DNNs	FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
DRAM Security	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
Dynamic Frequency Scaling	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
dynamic resource management	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems Leveraging Dynamic Resource Management for Energy Efficiency: To Speed-up or To Green-up
E
eBPF	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
Edge AI	FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining QYOLO: Lightweight Object Detection via Quantum Inspired Shared Channel Mixing
eFPGA	LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
Emerging Memory Technologies	Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
End-to-End Latency	Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
Energy efficiency	Leveraging Dynamic Resource Management for Energy Efficiency: To Speed-up or To Green-up Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method Implementation and Acceleration of MLP-Based IDS for FPGA
epidemiology	Leveraging Dynamic Resource Management for Energy Efficiency: To Speed-up or To Green-up
Explainability	GPU-Efficient XAI Uncertainty Estimation for nnUNet
F
FARIMA	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
Fast Fourier Transform	A Comparative Study of Parallel Implementations of Short-Time Fourier Transform
Feature Pyramid Networks	QYOLO: Lightweight Object Detection via Quantum Inspired Shared Channel Mixing
Field-Programmable Gate Array (FPGA)	Hardware Design of a Low-Cost, DSP-Free, Spiking Neural Network for Edge Devices
FMA data parallelism tensor parallelism NVLink all-reduce	Parallelizing Deep Learning: A Unified Study of CPU and GPU Partitioning Strategies, Bottlenecks, and Design Principles
FPGA	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning Implementation and Acceleration of MLP-Based IDS for FPGA LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
FPGAs	FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Fractional Brownian Motion	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
G
GEMM	Cross-Platform MLIR Based GEMM Micro-Kernel Generation
Geophysical Inverse Problems	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
GFLOPS	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC
Ghost Cell Halo Exchange	MPI-Based 3D Anisotropic RTM with Fletcher's Method and Ghost Cell Halo Exchange
GPU	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs GPU-Efficient XAI Uncertainty Estimation for nnUNet
GPU acceleration	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
GPU Architecture	HOOP: Hint based Out of Order Processing for GPGPUs via Per-Kernel Dependency Analysis
GPU computing	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method Design and Evaluation of Continuous Synthetic Data Pipelines for Vision Pre-training
GPU Partitioning	Predicting the Effectiveness of GPU Sharing for AI Inference on Aurora
GPU Sharing	Predicting the Effectiveness of GPU Sharing for AI Inference on Aurora
GPU Utilization	HOOP: Hint based Out of Order Processing for GPGPUs via Per-Kernel Dependency Analysis
Green HPC	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
H
Hardware-Software Co-Design	FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Heterogeneous Memory Systems	Assessing Arm SPE for Automatic Data Placement in Heterogeneous Memory Systems
high performance	Cross-Platform MLIR Based GEMM Micro-Kernel Generation
High performance computing	Phoning Home: Repatriating output from cloud jobs with a user-level, provider-agnostic data transfer tool
High-Performance Computing	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework Leveraging Dynamic Resource Management for Energy Efficiency: To Speed-up or To Green-up Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
High-performance computing (HPC)	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method
HIP	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
HPC	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC YABLT: Modeling Memory Bandwidth Effects by Limiting Bandwidth Availability A Methodology for System-Scale I/O Pattern Taxonomy for HPC Workloads
HPC job	Evaluating Runtime Prediction and Conservative Walltime Policies in HPC Systems
hyperspectral imaging	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
I
I/O	A Methodology for System-Scale I/O Pattern Taxonomy for HPC Workloads
Im2col	Zero-Copy GEMM-Based Fast Convolution
indoor localization	Resource-Aware Model Selection for Scalable Indoor Localization on HPC Platforms
industrial inspection	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
Instruction-Level Parallelism	HOOP: Hint based Out of Order Processing for GPGPUs via Per-Kernel Dependency Analysis
interference	New techniques to reduce cache interference in real-time mixed-criticality systems on multicore platforms
Interference profiling	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
Interference-aware scheduling	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
Intrusion detection	Implementation and Acceleration of MLP-Based IDS for FPGA
Irregular and graph workloads	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
K
kernel profiling	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
L
Large scale simulations	Phoning Home: Repatriating output from cloud jobs with a user-level, provider-agnostic data transfer tool
latency-constrained systems	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
Leaky Integrate and Fire (LIF)	Hardware Design of a Low-Cost, DSP-Free, Spiking Neural Network for Edge Devices
linear algebra	Cross-Platform MLIR Based GEMM Micro-Kernel Generation
Long-range dependence	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
M
malleability	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems
Matrix Multiplication	Zero-Copy GEMM-Based Fast Convolution
Medical Image Analysis	GPU-Efficient XAI Uncertainty Estimation for nnUNet
memory bandwidth roofline Amdahl’s law out-of-memory KV-	Parallelizing Deep Learning: A Unified Study of CPU and GPU Partitioning Strategies, Bottlenecks, and Design Principles
Memory Controller	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
micro-kernels	Cross-Platform MLIR Based GEMM Micro-Kernel Generation
Microarchitecture simulation	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
mixed-criticality	New techniques to reduce cache interference in real-time mixed-criticality systems on multicore platforms
MLIR	Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework Cross-Platform MLIR Based GEMM Micro-Kernel Generation
MLP accelerator	Implementation and Acceleration of MLP-Based IDS for FPGA
MNIST	Hardware Design of a Low-Cost, DSP-Free, Spiking Neural Network for Edge Devices
Model Compression	QYOLO: Lightweight Object Detection via Quantum Inspired Shared Channel Mixing
monitoring	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems
MPI	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
MPI Domain Decomposition	MPI-Based 3D Anisotropic RTM with Fletcher's Method and Ghost Cell Halo Exchange
multi-GPU	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
multicore	Analysis and Implementation Alternatives of Multi-grain Coherence Directories
N
near-data processing	Vector-In-Memory Architecture for Data-centric Applications
Neighborhood Collective	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
NSL-KDD dataset	Implementation and Acceleration of MLP-Based IDS for FPGA
Numerical Stability	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
O
Object Detection	QYOLO: Lightweight Object Detection via Quantum Inspired Shared Channel Mixing
Out-of-Order Execution	HOOP: Hint based Out of Order Processing for GPGPUs via Per-Kernel Dependency Analysis
P
parallel algorithms	A Comparative Study of Parallel Implementations of Short-Time Fourier Transform
Parallelization	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method
pattern	A Methodology for System-Scale I/O Pattern Taxonomy for HPC Workloads
Performance	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC
performance and scaling analysis	A Comparative Study of Parallel Implementations of Short-Time Fourier Transform
Performance Evaluation	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations Predicting the Effectiveness of GPU Sharing for AI Inference on Aurora The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
PRAC	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
Proactive VM migration	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
Programmable Logic	Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
PyTorch	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs Offloading Floating-Point Based Collective Operations to Programmable Logic for Distributed Learning
Q
Q-function	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
Quantum Machine Learning	QYOLO: Lightweight Object Detection via Quantum Inspired Shared Channel Mixing
R
real-time	New techniques to reduce cache interference in real-time mixed-criticality systems on multicore platforms
real-time processing	Architecture-Aware GPU Acceleration for Scalable Real-Time Industrial Hyperspectral Classification
reconfigurable instructions	LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
Reduced Precision	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
Reinforcement Learning	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
Resource management	Evaluating Runtime Prediction and Conservative Walltime Policies in HPC Systems
RISC-V	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC Implementation and Acceleration of MLP-Based IDS for FPGA LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
RISC-V Vector extension	Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework
ROCm	Beyond Throughput: Cross-Vendor Kernel-Level Characterization of DNN on modern GPUs
RowHammer	ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
Runtime prediction	Evaluating Runtime Prediction and Conservative Walltime Policies in HPC Systems
S
SBCs	Between Customization and Constraint: Performance, Scalability, and Software Readiness of RISC-V for HPC
Scalable Computing	Resource-Aware Model Selection for Scalable Indoor Localization on HPC Platforms
Seismic RTM (Reverse Time Migration)	MPI-Based 3D Anisotropic RTM with Fletcher's Method and Ghost Cell Halo Exchange
Seismic wave propagation	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method
Shared Memory	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
short-time Fourier transform	A Comparative Study of Parallel Implementations of Short-Time Fourier Transform
SIMD vectorization	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method
SLA compliance	Calibrated Multi-Step CPU Usage Forecasting via Fractional Brownian Motion-Driven FARIMA for Proactive VM Migration
Slurm	A Semi-Autonomous Monitoring Environment for Malleable HPC Systems
soft instruction	LUTstructions: Fast-Reconfigurable FPGA-Based Instructions
Solid-State Drives(SSD)	Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
sparse directory	Analysis and Implementation Alternatives of Multi-grain Coherence Directories
Spectral-finite-element method	Speedup and Energy benchmarks of GPU and SIMD spectral finite-element method
Spiking Neural Network (SNN)	Hardware Design of a Low-Cost, DSP-Free, Spiking Neural Network for Edge Devices
Spot instances	Phoning Home: Repatriating output from cloud jobs with a user-level, provider-agnostic data transfer tool
stablecoin	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
Storage Systems	Phoning Home: Repatriating output from cloud jobs with a user-level, provider-agnostic data transfer tool Dissecting End‑to‑End SSD I/O Latency in Storage Systems: Cross‑Layer Bottlenecks and Technology Trade‑offs
Sustainable Software	Optimization of Resource Efficiency in HPC: Exploiting Reduced Precision in Geophysical Simulations
Synthetic Data Generation	Design and Evaluation of Continuous Synthetic Data Pipelines for Vision Pre-training
System-level instrumentation	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
SystemTap	Cross-Application Interference Profiling in Consolidated Cloud Servers: Improving Portability, Overhead and Fidelity in IntP
T
taxonomy	A Methodology for System-Scale I/O Pattern Taxonomy for HPC Workloads
token escrow	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
U
Uncertainty Estimation	GPU-Efficient XAI Uncertainty Estimation for nnUNet
Upper-bound analysis	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
V
Value-at-Risk	The Volatility Tax: Quantifying Token-Escrow Risk in Decentralised Compute Markets
Virtual Topology	Exploiting Virtual Topology for Load- and Communication-Aware Neighborhood Collectives
W
walltime	Evaluating Runtime Prediction and Conservative Walltime Policies in HPC Systems
Warp Scheduling	HOOP: Hint based Out of Order Processing for GPGPUs via Per-Kernel Dependency Analysis
WiFi finger-printing	Resource-Aware Model Selection for Scalable Indoor Localization on HPC Platforms
Workload characterization	The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction
X
xDSL	Automatic Generation of Portable RVV Micro-Kernels through a Hybrid MLIR--xDSL Compilation Framework

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