ABSTRACT. Solid‑state drive (SSD) performance remains a key bottleneck in modern systems, impacting data‑intensive workloads such as LLM training, high‑throughput inference, and real‑time analytics. Although considerable industry effort has been devoted to replacing NAND flash with faster storage media, the resulting impact on end‑to‑end SSD latency is often insufficiently examined. This paper presents a systematic breakdown of storage latency across the storage‑cell, interface, and software layers. We first quantify the contribution of NAND flash access latency and demonstrate that beyond a certain reduction in device‑level access time, system‑level performance reaches saturation, yielding diminishing returns from further device improvements. Through a design‑space exploration, we evaluate the impact of device‑level enhancements (storage‑cell access time), interface‑level optimizations (flash interface characteristics), and software‑level techniques (page allocation policies). We further investigate emerging memory technologies, highlighting their trade‑offs in latency, cost, and energy. Taken together, our findings offer practical guidance for storage‑system designers, emphasizing that effective SSD optimization requires cross-layer consideration of both hardware and software, rather than faster devices alone.

ABSTRACT. As High-Performance Computing (HPC) races towards Exascale, I/O bottlenecks threaten to throttle the performance of data-intensive applications. Multiple paths have been explored in the literature to optimize I/O, such as I/O-awareness in job scheduling algorithms or data prefetching on a caching layer. However, these techniques require a systematic collection of information about the I/O behavior of applications. In this paper, we propose a methodology to classify data access patterns from I/O traces through three lenses: temporality, periodicity, and metadata load. With the instantiation of our methodology through CLASSIO, a Python library, we are able to detect I/O behaviors that are relevant to the deployment of I/O optimizations at a system scale. We validate CLASSIO on two datasets from top-tier supercomputers and show that our methodology is able to reveal noteworthy correlations, such as near-permanent accesses with larger data writes, that can help better understand how I/O are performed and identify patterns useful for I/O optimizations.

ABSTRACT. General Matrix Multiplication (GEMM) is a critical operation for several high-performance applications, and AI Models. To improve GEMM performance, optimized linear algebra libraries, such as OpenBLAS and BLIS, have been designed for a wide range of architectures. These are generally implemented as nested loops around a micro-kernel that performs the core computations and is hand-tuned to achieve maximum throughput. However, manually writing a micro-kernel requires significant effort and specialized knowledge of the specific hardware capabilities. In this paper, we present a cross-platform MLIR-based approach for automatically generating micro-kernels across a range of architectures. Our framework progressively lowers the micro-kernel via MLIR and LLVM backends to generate optimized code for the underlying hardware, thereby reducing micro-kernel design effort. Our generator supports masked edge-case handling and widening instructions. We evaluate our approach on Intel Xeon, AMD EPYC, Apple, and RISC-V Spacemit X60 architecture across different instruction sets. Experimental results show that it can consistently match and sometimes outperform manually written micro-kernels and other state-of-the-art automatic generators, achieving speedups of around 1.07x over BLIS on Spacemit X60 and staying within 5% of BLIS on Apple M4 and AMD EPYC, and within 10% on Intel CPUs.

ABSTRACT. Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors. Assessing the accuracy of numerous approximate multiplier designs across diverse DNN models and large-scale datasets remains challenging due to prohibitive evaluation times. This overhead primarily stems from the slow emulation of approximate multiplier behavior using look-up tables (LUTs) on CPU and GPU platforms. Moreover, the resulting accuracy degradation must be carefully quantified and, if necessary, mitigated (e.g., through retraining), further increasing the overall evaluation cost.

To address these challenges, we propose FAME, an FPGA-based platform for evaluating approximate multipliers. The platform exploits the reconfigurable logic of Field-Programmable Gate Arrays (FPGAs) to implement approximate multipliers directly in hardware, eliminating the need for LUT-based emulation on CPU/GPU platforms and thereby enabling efficient DNN inference while significantly reducing evaluation time on large datasets. Furthermore, we introduce a pattern-guided DNN retraining technique to mitigate accuracy degradation induced by approximate multipliers. Specifically, retraining is guided by multiplier-specific patterns to effectively recover potential accuracy losses. We evaluate FAME using two DNN models, ResNet-18 and MobileNetV2, on the ImageNet dataset across 27 approximate multipliers. During inference, our approach achieves up to a 3.47× speedup in approximate multiplier evaluation compared to prior LUT-based emulation methods. Furthermore, the proposed retraining technique improves accuracy by up to 65.5% over existing retraining approaches for the evaluated multipliers. The code is publicly available at: https://github.com/gicLAB/FAME

ABSTRACT. This paper presents ZConv, a new general matrix-matrix multiplication (GEMM)-based convolution formulation for central processing unit (CPU) architectures that eliminates data copies by exploiting the dimension and stride parameters of GEMM library calls. Unlike prior approaches, which reduce convolution to GEMM through Image-to-Column (Im2col) transformations or smaller data copies, this formulation achieves zero-copy execution. An extended version with minimal memory overhead further supports dilated and grouped convolutions, covering most convolution configurations. Extensive evaluation across a large dataset of convolutional layers demonstrates performance that is competitive with state-of-the-art implementations and superior to other published methods. When integrated into PyTorch, the approach yields end-to-end model speedups of up to 1.47x.

ABSTRACT. Branch mispredictions and data-cache misses are usually evaluated as separate bottlenecks: studies report perfect-branch or perfect-cache speedups as isolated upper bounds and often treat their product as the joint ceiling. In irregular workloads, however, hard-to-predict branches and cache-missing loads often appear in the same hot loops. Removing only one penalty can expose the other: faster memory lets the core reach mispredicted branches sooner, while better branch prediction leaves more long-latency loads occupying the out-of-order window. We call this interaction symbiotic stall latency (SSL).

This paper quantifies when isolated ceilings fail using joint speedup synergy (JSS), the observed joint perfect-branch/perfect-cache speedup divided by the product of the two isolated speedups. Values above one mean independent-ceiling analysis understates attainable gain. Across 53 simulated workloads, 70% show measurable coupling (JSS > 1), although many are close to unity; design-relevant cases concentrate among higher- pressure workloads. With a conservative threshold, 40% exceed the independence product by more than 6%, and kernels with SSO > 20 show JSS from 1.23 to 3.29. We introduce symbiotic stall opportunity (SSO), a lightweight MPKI-based screen for identifying workloads that merit full joint simulation.

We map high-SSO workloads to four recurring software patterns: neighbor access, hash lookup, linked-structure traversal, and data-dependent modification. We then connect SSL to reorder-buffer occupancy, squash rate, and commit starvation under isolated perfect modes. The result is an evaluation methodology: use SSO to screen, use JSS to validate, and report conditional branch-after-cache and cache-after-branch gains when evaluating branch predictors, prefetchers, caches, or coupled branch/memory mechanisms. Our contribution is a measurement framework showing when isolated perfect modes are adequate and when they understate joint performance headroom.

ABSTRACT. Distributing iterative stencil computations across HPC nodes requires careful design of inter-process communication, particularly to overlap halo exchanges with interior computation using ghost cells. Whether such overlap achieves genuine communication masking depends on the relationship between problem size, partitioning topology, and network bandwidth. This paper presents a distributed MPI implementation of the Fletcher RTM seismic application using 3D block decomposition and asynchronous ghost cell communication, with GPU acceleration via CUDA. Experiments on real HPC clusters reveal two sharply contrasting regimes: CPU-only machines achieve near-perfect communication hiding (75--87% compute load) due to modest floating-point throughput, while GPU-equipped clusters invert the bottleneck entirely: the RTX4070 accelerator outpaces a 1Gbps interconnect, and stalls compute load near 20% regardless of problem size. Calibrated SimGrid SMPI simulations demonstrate a smooth, bandwidth-driven transition from communication-bound to computation-bound behavior, with GPU compute load rising from \approx20% at 1Gbps to \approx75--80% at 10Gbps and \approx85--90% at 100Gbps. Partitioning topology is shown to be as decisive as bandwidth: prime process counts force slice decompositions that yield negative speedup relative to the single-node baseline, with a 5-worker configuration falling below the 3870 MSamples/s baseline while an 8-worker configuration reaches 8309 MSamples/s (10Gbps) and 9374 MSamples/s (100Gbps). Together, these results establish that interconnection bandwidth and the partitioning topology are co-determining factors for ghost cell masking effectiveness in distributed stencil applications.

ABSTRACT. Numerical simulation plays a central role in geo- sciences. The study of complex phenomena such as earthquakes requires large-scale 3D computations. Codes like EFISPEC3D, developed by the BRGM (French Geological Survey), rely on the Spectral-Finite-Element Method (SEM) — a high-order variant of the classical Finite-Element Method (FEM) that achieves greater accuracy without requiring finer meshes. However, these simulations remain computationally intensive, making paral- lelization essential. On CPUs, automatic vectorization by compilers has proven insufficient for EFISPEC3D. The compute kernel was extracted to study its optimization using explicit vectorization (SIMD intrinsics) on various CPU platforms. Results show significant performance improvements depending on the SIMD vector length and on the memory bandwidth. In this work, we present and compare two GPU implementations of the EFISPEC3D kernel: one derived from the existing CPU vectorization strategy and the other based on a conventional GPU parallelization strategy, following the approach used in the SPECFEM code. We show that GPU parallelization offers significantly better performance and energy efficiency, as the GPU kernel implementation achieves a substantially higher speedup than the vectorized CPU kernel. Based on these results, the entire simulation has since been ported to GPU, yielding considerably higher overall accelerations and further demon- strating the potential of GPU computing for large-scale seismic wave propagation codes.

ABSTRACT. Large-scale indoor localization is increasingly needed in campuses, smart buildings, factories, and digital-twin infrastructures, where wireless conditions, access-point deployments, and spatial layouts evolve over time. Such systems must be accurate, extendable, and maintainable, allowing new buildings, floors, rooms, and service areas to be added without retraining a monolithic model. Modular learning-based localization supports this goal by assigning independent models to buildings, floors, and fine-grained spatial regions. However, this extendability introduces a high-performance inference challenge: each query may require selecting and executing among hundreds or thousands of local models, making exhaustive inference costly in computation, accelerator memory residency, model loading, and scheduling. This paper presents a resource-aware modular inference framework for WiFi fingerprint-based indoor localization on high-performance and distributed computing platforms. The framework organizes local autoencoder models into a building-floor-spot hierarchy and formulates localization as model selection over a large pretrained model ensemble. To reduce inference cost under resource constraints, we introduce two lightweight execution-pruning strategies: Hierarchical Candidate Pruning, which performs coarse-to-fine model selection, and Trajectory-Aware Pruning, which uses temporal locality in user movement to restrict inference to spatially plausible neighboring models. Experiments on a real-world dataset demonstrate that the proposed framework delivers scalable inference without sacrificing localization quality. Compared with exhaustive evaluation over 735 spot models, Hierarchical Candidate Pruning requires only 67 model evaluations, while Trajectory-Aware Pruning reduces this number to just 10, cutting model executions by 98.6\%. Under constrained-memory execution, the same pruning strategies also lower latency by minimizing inactive model loading, highlighting their potential for extendable, high-performance, and distributed indoor localization services.

ABSTRACT. Line-scan hyperspectral imaging systems are increasingly being adopted for industrial inspection and sorting applications, where practical deployment depends on satisfying strict real-time processing constraints imposed by continuous conveyor-based acquisition. Unlike conventional remote sensing scenarios that process complete hyperspectral data cubes offline, industrial push-broom sensors deliver data as a continuous high-dimensional stream of spatial-spectral lines subject to hard latency deadlines. Under these conditions, hyperspectral classification becomes a latency-constrained streaming workload in which spectral vectors must be processed continuously under deterministic timing constraints. In this work, we consider a real-time processing pipeline composed of spectral preprocessing followed by Spectral Angle Mapper (SAM) classification, and propose a hardware-aware GPU implementation optimized for deterministic low-latency execution. The work focuses on the architectural optimization of streaming hyperspectral processing through successive kernel refinements, asynchronous stream-based execution, and communication-aware data movement strategies. We analyze the interplay between computational throughput, memory hierarchy efficiency, synchronization overhead, and host-device communication under continuous industrial acquisition conditions. Experimental results demonstrate that, for a Specim FX17 hyperspectral line-scan sensor operating at 670 fps over the full spectral range and producing lines of 640 spatial pixels across 224 spectral bands, corresponding to a deterministic processing budget of only 1.49ms per acquired line, the proposed implementation leaves more than 97\% of the available processing time free for additional pipeline stages in a window-based streaming configuration involving four spectrally similar materials.

Experimental results demonstrate that, for a Specim FX17 hyperspectral line-scan sensor operating at 670 lines per second over the full spectral range and producing lines of 640 spatial pixels across 224 spectral bands, corresponding to a deterministic processing budget of only 1.49ms per acquired line, the optimized GPU implementation requires only 1.04% of the available real-time budget for preprocessing and classification, leaving nearly 99% of the processing time available for additional pipeline stages in a window-based streaming configuration involving four spectrally similar materials plus conveyor-belt background discrimination.