ABSTRACT. Collective operations play a major role in the high-performance computing space. As key components of network-connected inter-node communication and computation, these collective operations can be a significant source of overhead when executing distributed applications. With a focus on distributed learning workloads, this paper examines offloading these operations to dedicated hardware resources via programmable logic to improve resource availability at the compute nodes. With the bump-on-the-wire approach, our design is self-contained, with the ability to perform the complete computations and relevant intermediate communications without the involvement of software. Distributed learning is currently focused on utilizing lower-precision floating-point representations to achieve lower data loads while maintaining training precision. Our hardware is able to natively perform AllReduce sum and average operations, which are key in these distributed learning applications, on the standard IEEE 754 32-bit floating-point representations as well as on specialized 16-bit floating-point representations, namely BFloat16 and DLFloat. This allows distributed learning applications to dynamically switch between the supported floating-point representations while reaping the benefits of deterministic latency. In terms of wide adaptability, our hardware is accessible through the PyTorch Distributed Learning Library. We will demonstrate the compatibility of our design with distributed learning workloads and the comparable runtime latency against popular collective operation libraries. Compared to our previous work, we achieved up to 11x overall latency reductions for lower data load, while the hardware compute pipeline maintains near-deterministic latency under 1.7 µs. Future work for this design will focus on improving overall throughput and expanding compatibility with floating-point representations while maintaining deterministic latency.

ABSTRACT. Modern chip multiprocessors continue to scale in core count and private cache capacity, increasing storage pressure on coherence directories. Prior work has addressed this challenge through compressed sharing information, sparse directories, and coarse-grain tracking. Multi-grain directories reduce storage requirements while preserving tracking precision by supporting dual granularity: block and region. At region granularity, multiple private blocks held by the same core are represented by a single entry. Yet, existing designs rely on complex structures that hinder practical implementation, and their trade-offs remain insufficiently characterized.

This work provides a detailed characterization of multi-grain coherence directories. Unlike conventional single-grain designs, these directories impose constraints on how blocks map to distributed shared cache banks. We analyze alternative mappings and their implications for directory organization. Based on this analysis, we introduce minimal modifications that enable entry merging comparable to state-of-the-art multi-grain designs without requiring complex structures. Our results show that this simplified design matches state-of-the-art performance while significantly reducing implementation complexity.

ABSTRACT. Modern GPUs have emerged as the preferred platform for accelerating scientific computing and general-purpose workloads, primarily due to their ability to offer high thread-level parallelism within constrained energy budgets. However, these general-purpose workloads often struggle to fully exploit GPU resources, limiting their potential performance gains. This limitation arises from the limited data-level parallelism, high memory intensity and irregular access patterns characteristic of these applications. While prior work has explored out-of-order (OoO) execution to exploit instruction-level parallelism in GPUs, existing approaches incur substantial hardware overhead due to per-warp dependency tracking and complex scheduling logic.

To address these challenges, we propose HOOP, a low-overhead, energy-efficient microarchitecture designed to enable out-of-order scheduling in GPGPUs. HOOP fundamentally rethinks dependency analysis in GPUs and leverages a key observation that warps within a kernel share an identical instruction stream. HOOP achieves out-of-order scheduling through a hardware Hint Generation Unit that identifies independent instructions within execution kernels, coupled with microarchitectural enhancements that leverage these hints to enable out-of-order instruction execution. HOOP is a fully out-of-order, non-speculative microarchitecture for GPGPUs that overcomes limited data-level parallelism in non-graphics workloads by exploiting inherent instruction-level parallelism. Our evaluations with HOOP across a set of 29 varied benchmarks show a 9.8% speedup on average with a maximum performance gain up to 48% with respect to baseline, along with a 4% speedup over the current state-of-the-art out-of-order GPU design. Additionally, HOOP improves energy-delay product (EDP) by 5.4% on average. By performing dependency analysis once per kernel rather than per warp, HOOP demonstrates that efficient OoO execution in GPUs scales with SM count rather than against it.

ABSTRACT. Spiking neural networks (SNNs) offer a promising event-driven paradigm for energy-efficient edge computing. While dedicated neuromorphic ASICs provide extreme energy efficiency, Field-Programmable Gate Arrays (FPGAs) remain essential for rapid architectural prototyping and flexible, application-specific customization. To minimize hardware resource utilization without sacrificing deterministic behavior, this paper presents a low-cost, low-power, fully DSP-free time-division multiplexed (TDM) SNN accelerator. The architecture integrates a deterministic ramp-based spike encoder with a leaky integrate-and-fire (LIF) neuron utilizing a shift-based leak mechanism. A centralized finite state machine ensures strict cycle-accurate alignment. To demonstrate scalability on non-trivial spatial patterns, the design is evaluated on the MNIST and Fashion-MNIST datasets. The system features an event-driven early-exit classification mechanism that dynamically adapts to workload complexity. Synthesized on a Xilinx Artix-7 AC701 (xc7a200tfbg676-2) FPGA, the highly compact design utilizes only 6,070 LUTs, 8,855 FFs and consumes 0.274 W. Operating at 150 MHz, the early-exit mechanism reduces the average inference window to just 7.55 timesteps, yielding a 94.24\% accuracy, an average throughput of 13.70 images per second, and an average energy consumption of 20 mJ per inference for the MNIST dataset. Additionally the system was tested on the more complex Fashion-MNIST dataset. These results validate a highly practical, workload-aware framework for mapping complex, resource-constrained neuromorphic architectures to edge hardware.

ABSTRACT. The growing diversification of high-performance processor architectures, together with the increasing adoption of heterogeneous memory systems, introduces new challenges for performance portability and efficient memory management. As Arm-based platforms gain relevance in the HPC landscape and technologies such as HBM and CXL memory expansion become more widespread, software mechanisms capable of automatically exploiting memory heterogeneity are increasingly important. Precise sampled hardware events have proven valuable for characterizing memory behavior on several processor families; however, their use on Arm platforms has only recently become feasible through the introduction of the Statistical Profiling Extension (SPE). In this work, we extend the ecoHMEM automatic data-placement framework to support Arm-based systems by leveraging SPE as a source of precise memory-access information. We design and implement the required profiling infrastructure, discussing the relevant tradeoffs. Experimental evaluation on an Arm system with emulated memory heterogeneity demonstrates the feasibility of using SPE within a data-placement workflow, yielding performance improvements of up to 22% with respect to mainstream NUMA strategies.

ABSTRACT. Modern cloud data centers consolidate diverse applications on shared hosts, where resource contention among co-located applications generates cross-application interference that degrades performance and compromises quality of service. IntP, a system-level interference profiler introduced in 2022, addresses this by combining kernel instrumentation and hardware performance counters into a seven-metric interference fingerprint per application, enabling interference-aware consolidation. Its original implementation, however, relies on kernel and hardware interfaces that are no longer compatible with modern Linux systems. This paper presents a modernization of IntP across multiple instrumentation substrates, improving portability across Linux kernel generations and instrumentation ABIs while preserving measurement fidelity and maintaining low overhead. We redesigned the profiling infrastructure of the original SystemTap version around state-of-the-art instrumentation mechanisms and compared it with two modern versions: a portable C version on stable userspace interfaces and an eBPF/CO-RE version. Experimental results show that the two modern versions reproduce the legacy interference fingerprint while improving portability, reliability, and measurement fidelity, within a ±3 % overhead envelope on CPU- and memory-bound reference loads. Our evaluation also characterizes the portability, overhead, and fidelity trade-offs across these substrates, providing substrate-aware deployment guidance.

ABSTRACT. The predominance of double-precision arithmetic in scientific applications imposes severe computational costs, challenging the sustainability of High-Performance Computing (HPC). This work investigates the impact of the reduced precision paradigm as a strategy to enable Green HPC. The main objective is to analyze the consequences of numerical precision reduction (such as the transition from Float64 to Float32) on computational performance, encompassing execution time and memory usage, and on the accuracy of scientific results. Since validating these strategies solely through theory is insufficient, a practical case study was conducted using high-performance geophysical simulations from the open-source Fatiando a Terra ecosystem. The research was operationalized by modifying data types (dtypes) in matrix operations performed by libraries such as NumPy and Numba, leveraging hardware optimizations in modern architectures. The methodology evaluates the trade-off between efficiency and scientific validity on two fronts: (1) controlled benchmarking experiments on potential field algorithms, and (2) a real-world application involving massive geospatial data for hyperparameter optimization. Results demonstrate that, while precision reduction offers significant performance gains, its feasibility is strictly governed by the numerical resilience of the underlying mathematical formulation, especially by the presence of regularization. This study contributes to computational geophysics, particularly in the domain of potential fields, by establishing empirical guidelines for the safe adoption of low-precision arithmetic in solving inverse problems and spatial interpolation, preventing catastrophic cancellations in critical Earth modeling workflows.

ABSTRACT. The rapid advancement of object detection architectures has positioned single-stage detectors as the dominant solution for real-time visual perception. A primary source of computational overhead in these models lies in the deep backbone stages, where C2f bottleneck modules at high stride levels accumulate a disproportionate share of parameters due to quadratic scaling with channel width. This work introduces QYOLO, a quantum-inspired classical channel mixing framework that achieves genuine architectural compression by replacing the two deepest backbone C2f modules at P4/16 (512 channels) and P5/32 (1024 channels) with a compact QMixBlock. The proposed block performs global channel recalibration through a sinusoidal mixing mechanism with shared learnable parameters across both backbone stages, enforcing consistent channel importance without requiring independent per-stage parameter sets. The neck and detection head remain fully classical and unchanged. Evaluation on the VisDrone2019 benchmark demonstrates that QYOLOv8n achieves a 20.2% reduction in parameter count (3.01M to 2.40M) and 12.3% GFLOPs reduction with only 0.4 pp mAP@50 degradation. QYOLOv8s achieves 21.8% reduction with 0.1 pp degradation. When combined with knowledge distillation, full accuracy parity is recovered at no cost to compression. An expanded backbone-plus-neck variant achieved 38–41% reduction at the cost of greater accuracy degradation, motivating the backbone-only final design.

ABSTRACT. Decentralised compute marketplaces are increasingly proposed as an alternative to hyperscale cloud, but nearly all of them require buyers to lock a platform-specific token as escrow. Buyers whose costs are denominated in a stable currency are therefore exposed to token-price risk that is entirely independent of whether the compute contract is executed correctly. We call the cost of this involuntary exposure the volatility tax, and we measure it. Using 365 days of price data for five marketplace tokens (AKT, GLM, RLC, ATH, RNDR), we find that for a EUR 500 30-day escrow the 95% Value-at-Risk ranges from EUR 178 (GLM) to EUR 273 (ATH); the certainty-equivalent cost to a moderately risk-averse buyer (gamma = 3) is EUR 69, or 13.8% of escrow value. The exposure is large but highly concentrated: across 1,426 active Akash leases, 4.4% carry at least 62.9% of an aggregate VaR of EUR 31,000-53,000 depending on the escrow regime, while the median lease faces negligible exposure. We assess the estimates with GARCH(1,1), Kupiec backtests, bootstrap confidence intervals and Lo-MacKinlay variance-ratio tests, and note that our observation window covers normal-to-moderate conditions and so likely understates stressed-regime tails. Directly measured alternatives reduce or remove the exposure: euro-denominated stablecoin escrow (EURC, daily sigma = 0.135%) cuts VaR by roughly 40x and USDC by roughly 15x, while fiat settlement eliminates it. Crucially, this substitution is architecturally independent of the consensus protocol: a marketplace can adopt it without changing its blockchain, its governance model, or its permissionless character.

ABSTRACT. Consolidating virtual machines onto fewer servers raises the per-server load and, with it, the risk of congestion. Because live migration takes seconds to tens of seconds, a sufficiently consolidated cloud reaches a regime in which reacting to congestion already observed is too late and congestion must instead be anticipated. We first delimit that regime qualitatively, separating a Static, a Reactive and a Proactive operating region, to establish when forecasting becomes necessary to meet the SLA rather than merely beneficial, and then supply the forecasting tools that operating in the Proactive region requires. Real traces from an academic private cloud reveal strong long-range dependence (Hurst parameter H in [0.80, 0.99]), motivating FARIMA(p, d, 0) models linked to fractional Brownian motion through H = d + 0.5. Beyond one-step accuracy, we derive the k-step prediction-error variance in closed form, yielding prediction intervals at operationally relevant horizons (up to 30 s), and use the Q-function to turn forecasts into threshold-exceedance probabilities. Empirically these analytical intervals are well calibrated where those of the non-fractional counterpart are over-dispersed. For risk-based decisions this property matters more than lower point error. The intervals also lower the model-implied congestion risk by up to 2.5 percentage points, concentrated where the predicted load approaches but has not yet crossed the threshold. This paper thus provides a calibrated forecasting layer, a first step toward a proactive closed-loop migration policy.

ABSTRACT. Mixed-criticality systems are common in industries such as aerospace, automotive, medical, telecommunications, defense, energy and critical infrastructure. They require the coexistence of applications with different levels of criticality and the fulfillment of real-time requirements. Cache memory, as a shared resource, poses significant interference problems, affecting the performance and data access times of real-time applications. This paper addresses cache memory interference in mixed-criticality systems, especially in MpSoC architectures, by proposing new cache memory management techniques that outperform existing methods in mitigating the interference of non-critical tasks on real-time critical ones. Using the proposed techniques and cache simulator, this paper aims to improve the reliability of mixed-criticality systems in various industrial sectors.

ABSTRACT. Real-time implementation of neural networks for network security presents severe computational challenges on embedded systems. This paper proposes a hardware/software (HW/SW) co-design approach to accelerate an Intrusion Detection System utilizing a Multi-Layer Perceptron. We introduce a custom accelerator for an FPGA platform, deployed alongside the open-source RV32IMF RISC-V processor, "Hornet". The accelerator design enables memory localization and parallelization of floating-point multiplications, thereby eliminating latency bottlenecks. Results show that the Hornet with the accelerator delivers a 63.8x speedup in single-input inference latency compared to pure software C execution on the Hornet core. While this parallelization inherently increases LUT and FF footprints, the localized memory architecture reduces BRAM utilization by 16.8%. The proposed HW/SW design maintains a robust overall accuracy of 78.86%, exhibiting an insignificant 0.02% drop from the 78.88% baseline established by the golden model execution on PC. Furthermore, the accelerator achieves a remarkable 97.1% reduction in energy consumption per inference. Although a slight reduction in the macro F1-score is observed as an inherent trade-off, this work demonstrates a highly efficient deployment strategy for real-time cybersecurity acceleration.

ABSTRACT. General-purpose processors feature a limited number of instructions based on an instruction set. They can be numerous, such as with vector extensions that include hundreds or thousands of instructions, but this comes at a cost; they are often unable to express arbitrary tasks efficiently. This paper explores the concept of having reconfigurable instructions by incorporating reconfigurable areas in a softcore. It follows a relatively new computing paradigm for seamlessly loading instruction implementation-carrying bitstreams from main memory. The resulting softcore is entirely evaluated on an FPGA, essentially having an FPGA-on-FPGA for the instruction implementations, with no notable operating frequency overhead. This is achieved with a custom FPGA architecture, which is tailored towards low-latency for custom instructions and wide reconfiguration, as well as a soft implementation for the purposes of architectural exploration. All code is open-source to foster further research on reconfigurable instructions.

ABSTRACT. RowHammer vulnerability continues to intensify with DRAM scaling, reducing the activation threshold needed to induce bitflips and rendering existing defenses such as TRR, ECC, and refresh-based mechanisms vulnerable to sophisticated multi-bank hammering patterns. This work presents ARTA, a lightweight reinforcement-learning-based throttling mechanism that detects and suppresses RowHammer activity by monitoring fine-grained memory access behavior within the DRAM refresh window (t_REFW) and dynamically adjusting core throughput using a Q-learning frequency scaling governor. ARTA requires no DRAM-side hardware modification or offline training, using small SRAM structures in the memory controller — a per-core, per-bank FIFO queue (CBF) and a compact Q-table — for immediate deployment. Our evaluation shows that ARTA eliminates all bitflips at N_BO values down to 64, reduces bitflips up to 22K times at N_BO of 20, and improves performance up to 73.6% over state-of-the-art mitigation mechanisms by limiting preventive action overheads for improved memory bandwidth throughput. These results demonstrate that adaptive RL-based throttling provides robust, scalable, and high-performance RowHammer mitigation for emerging DRAM systems.

ABSTRACT. Cross-vendor DNN training is reported as aggregate throughput, which identifies the faster platform but not the cause of any gap. Such a gap may arise from a hardware capability ceiling, a library inefficiency, or a framework abstraction overhead, yet no published kernel-level decomposition exists. We characterize DNN training on the NVIDIA H100 and the AMD MI300X by comparing PyTorch inside the vendor container against native CUDA and HIP implementations compiled from a single source tree. The native baseline removes the Python interpreter, the autograd engine, and the ATen operator dispatcher while retaining direct calls to cuDNN, cuBLAS, MIOpen, rocBLAS, NCCL, and RCCL. All experiments are conducted in FP32 with tensor-core math disabled. Fully-connected networks on MNIST, Fashion-MNIST, and CIFAR-10 probe dispatch latency without saturating compute; ResNet-50 on ImageNet-1K, evaluated from one to eight GPUs across batch sizes, is the primary compute-bound workload. For distributed training we propose a layer-aligned flat-bucket gradient synchronization scheme and evaluate it against PyTorch DDP under NCCL and RCCL. A power-cap sweep extends the analysis to energy per image and the energy-delay product(EDP). The flat-bucket scheme attains higher parallel-scaling efficiency than DDP on both platforms. The HIP port localizes the MI300X realized-versus-peak performance gap to library default heuristics on compute-bound stages and to on-chip data reuse on bandwidth-bound stages, not to the interconnect fabric or the roofline. Energy per image is convex in the per-GPU power cap. The interior minimum sits at 250\,W on the H100 and 550\,W on the MI300X and is identical across software stacks. The joule-per-image optimum is therefore set by the device voltage-frequency curve, not by the framework. The EDP knee, 50 to 200\,W above, separates energy-optimal from throughput-optimal operating points. To our knowledge, this is the first kernel-level PyTorch vs native characterization of DNN training that includes the AMD MI300X and that reports performance and energy jointly.

ABSTRACT. GPU-accelerated supercomputers increasingly host multiple workloads, yet individual applications rarely fully utilize the accelerator, leaving compute and memory resources idle while contributing to system power and queue occupancy. Enabling multiple workloads to share a single GPU tile through partitioning mechanisms, such as the use of multiple Compute Command Streamers (CCS) on Intel GPUs, can improve utilization, but whether sharing helps or hurts depends on the resource overlap between co-located applications, and evaluating all workload pairs requires O(n²) profiling runs that grow prohibitively as the workload set scales. We characterize six artificial intelligence (AI) inference workloads, OLMoE-1B-7B, Llama 3.1 8B, Qwen3-8B, BERT-Large, ResNet-50, and 3D U-Net, on the Intel Data Center GPU Max 1550 in the Aurora supercomputer. We first evaluate isolated execution across 1CCS, 2CCS, and 4CCS configurations, combining throughput, latency, power, and hardware-counter measurements. We then evaluate multi-tenant co-execution under 2CCS, in which two workloads concurrently share the same GPU tile, with one CCS partition assigned to each workload. Memory-bound workloads with sparse or bursty execution, such as OLMoE, retain over 90% throughput under 2CCS and are the most beneficial co-location partners, whereas compute- and bandwidth-saturated workloads, such as 3D U-Net, degrade under any partitioning configuration. Across 135 evaluated co-execution configurations, multi-tenant execution improves throughput-per-watt in 95.5% of cases, with a median gain of 1.22×, at a median latency cost of 1.51×. A gradient-boosted regression model trained on isolated single-tenant CCS profiles predicts per-workload co-execution slowdown with an R² of 0.931 and a mean absolute error of 0.027, reducing characterization cost from O(n²) pairwise measurements to O(n) standalone profiles.

ABSTRACT. The performance of modern day workloads is constrained by memory bandwidth availability: when memory bandwidth becomes saturated, execution units of the underlying hardware stall, resulting in a significant performance drop. In this context, accurately characterizing how an application responds to memory resource pressure is crucial to (1) appropriately dimension and codesign target platforms, (2) evaluate resilience under constrained memory scenarios, and (3) predict performance for emerging computing platforms. Existing approaches to evaluating bandwidth sensitivity have limited practical applicability, as they rely on either static analytical models, physical hardware modification, or require privileged operations, none of which are easily accessible to end users. To address these shortcomings, this paper presents YABLT, a bandwidth limitation tool that dynamically injects memory contention to facilitate performance analysis. YABLT allows users to specify the amount of bandwidth to be removed from the system, continuously self-profiling to adjust contention so that the targeted bandwidth reduction is met while other applications run concurrently. We evaluate YABLT on both microbenchmark and full applications, demonstrating its ability to infer performance with a mean absolute percentage error of 8.89% when predicting behavior on the same architecture and 14.26% when predicting across different architectures.

ABSTRACT. The short-time Fourier transform (STFT) computes the Fourier transform of a short-duration window of a longer signal, which characterizes how a frequency changes over time. While the Fourier transform algorithms, particularly the Fast Fourier Transform (FFT) algorithm, has been well developed to take advantage of parallel computing, there is limited work on the parallelization of short-time Fourier transform algorithms. In this study, two parallel short-time Fourier transform algorithms, one is FFT-based and the other a quasi-parallel feedforward algorithm, are implemented and analyzed. It is found that while the quasi-parallel algorithm outperforms in runtime under low concurrency settings, the FFT-based algorithm scales better and has lower memory usage. For each algorithm, three parallel approaches, shared-memory, distributed-memory and hybrid distributed-shared-memory, are compared. Profiling results show that all implementations are compute bound except for the hybrid feedforward algorithm, and that the distributed-memory variants incur significantly higher communication cost. Overall, this study demonstrates the space-time tradeoff in parallel implementations of the short-time Fourier transform, in which the FFT-based approach uses less memory while the quasi-parallel feedforward algorithm has lower runtime but higher serial fraction.

ABSTRACT. As more heterogeneous systems become mainstream in the era of Exascale computing, High-Performance Computing environments are increasingly exploring open, extensible architectures to satisfy power efficiency and domain specific customization demands. However, evaluating emerging instruction set architectures (ISAs) requires distinguishing instruction set abstractions from microarchitectural and compiler-level bottlenecks. In this work, we present an empirical study of low-power sub-10W TDP Single-Board Computer (SBC) microarchitectures: T-Head TH1520 (RISC-V Xuantie C910), Intel Celeron J4125 (x86 Goldmont Plus), and Broadcom BCM2711 (ARM Cortex-A72). We evaluate raw compute throughput, memory hierarchy latency, and inter-node scaling using HPL, DGEMM, STREAM, and NAS Parallel Benchmarks (NPB).

Results demonstrate that compiler optimization can improve relative performance by up to 10×; however, achieved throughput remains only 8.6\% of the C910’s theoretical 28.8 GFLOP/s vector peak. We showed performance is largely constrained by both software maturity and microarchitectural and establish an objective baseline for HPC RISC-V deployment and outline requirements for scalable adoption.

ABSTRACT. As the data volumes handled by applications continue to increase annually, the significance of Near-Data Processing (NDP) architectures grows. These applications are particularly vulnerable to the challenges posed by the memory wall. While numerous near-data architectures have been proposed, demonstrating substantial improvements across various metrics relevant to Big Data applications, their adoption is limited due to several challenges. Foremost among these challenges are issues related to programmability and integration. Most existing near-data designs lack sufficient support from compilers or tools, making tasks like scheduling and offloading of near-data logic and data mapping complex. In our study, we introduce Vector-In-Memory Architecture (VIMA), a near-data processing architecture that prioritizes programmability and extensibility while also delivering superior performance in terms of execution time and energy efficiency. Through cycle-accurate simulations, we demonstrate that by incorporating architectural elements such as a dedicated near-data cache memory and instruction buffer, a single-threaded VIMA achieves remarkable improvements in execution time. VIMA achieves speedups of up to 8x relative to a 16-thread x86 (Intel Skylake) baseline, while simultaneously reducing energy consumption by as much as 96% when handling common Big Data algorithms. We observed that these most significant gains are driven primarily by reuse-heavy workload patterns.

ABSTRACT. The scale and complexity of high-performance computing (HPC) and cloud infrastructures continue to increase, making resource management a central challenge for modern platforms. Static reservation models are increasingly inefficient for workloads whose resource requirements evolve during execution, such as dynamic workflows and malleable applications. This paper presents (Hidden-name), a semi-autonomous monitoring and decision-support environment for HPC systems with dynamic resource management. (Hidden-name) combines lightweight system monitoring, data analysis agents, anomaly detection, predictive components, and a malleability notifier that cooperates with an Intelligent Controller and Slurm. The proposed architecture supports resource allocation decisions without modifying Slurm, enabling applications to request expansions or contractions at runtime while preserving compatibility with production deployments. Experimental results on a real HPC platform show that starting malleable applications with one node and expanding them dynamically can reduce the workload makespan by 38.9\% with respect to a static execution scenario. In addition, we include a discussion section on malleability where indications are given of benefits and losses that may occur depending on which applications are used and when the reconfigurations are applied, which is not trivial.