PROGRAM FOR WEDNESDAY, JULY 2ND

ABSTRACT. An inductor modeling suitable for DC-DC converters is proposed in this paper. It consists of introducing an appropriate parallel resistance in order to account for inductor current ripple when averaging technique is employed. This allows the development of an improved averaged model for DC-DC converters, which takes into account inductor power losses due to current ripple phenomenon. The worth and effectiveness of the proposed modeling approach has been validated through a simulation study, which is performed in the Matlab-Simulink environment and refers to the case of a boost DC-DC converter.

ABSTRACT. Power converters based on Wide Bandgap Devices (WBD) are able to operate at once high-frequency and high-voltage. In such converters a short dead-time is advised. Mismatching between high-side and low-side propagation delays involves a long secure dead-time. We propose a topology based on a single low-side 2-channel digital isolator and one high-speed monolithically integrated level-shifter instead of two separate isolators. The translator has been implemented with a 1200V SiC JFET and 50V MOSFETs. At 240V input voltage and 100 kHz switching frequency, the level shifter propagation delay is 10ns with 1.85mA supply current thanks to a built-in current regulator. A 25ns dead-time can be safely set improving converter operations while reducing common mode signal propagation, size and price.

ABSTRACT. This paper presents a method of electro-thermal co-simulation for power electronic circuits made in a high voltage BiCMOS technology for automotive applications. The method allows the complete and correct modeling and optimization of high power analog circuits and guarantee robustness in fault conditions. The method was successfully applied on a low dropout linear voltage regulator, emphasizing the elements that influence the electro-thermal behavior of the circuit and its protection circuitry.

ABSTRACT. This paper illustrates the photon’s absorption phenomenon in 4H-SiC. It shows two-dimensional Optical Beam Induced Current measurements (2D-OBIC) in 4H-SiC bipolar diodes. Two different diode structures were studied: the first one is a circular MESA protected avalanche diode with an optical window, and the second structure is a PN diode protected with a junction termination extension layer. The results provided an image of the electric field distribution in the diode surface. These measurements validate the efficiency of the used protection. The effect of radius at the periphery of the diode was also studied. Structural defects are explored by a variation of photo-current at this local point.

ABSTRACT. Technology parameter variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. This presentation introduces the concept of “safe operation region” to allow an efficient analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.

ABSTRACT. Brain’s stunning speed, energy efficiency and massive parallelism makes it the ideal model for future high performance computation systems. Although human brain components are a million times slower than state of the art silicon industry components, they can perform 1016 operations per second while consuming less power than an electrical light bulb. In order to perform the same amount of computation with today’s most advanced computers, the output of an entire power station would be needed. In that sense, to obtain brain like computation, ultra-fast devices with ultra-low power consumption will have to be integrated in ultra-compact areas, achievable only if folded structure of brain cortex is mimicked.

ABSTRACT. We propose a method for the formal reset sequence verification for digital asynchronous circuits. First the traditional approach for the reset verification is discussed and the need for a novel solution is shown. The proposed method is based on the extension of the standard logic types with a multi-value logic type and a source code intrumentation method. The method is finally applied at an exemplary circuit fragment showing promising results.

ABSTRACT. A novel and simple circuit topology is presented for high-speed, floating, high voltage level shifters. It uses a current mirror plus latch circuit composed of two inverters. Simulations based on AMS 0.18 μm High Voltage (HV) CMOS Technology show this circuit to combine high speed, low power dissipation, and small layout area. The simulation results show the propagation delay to be below 150 ps for a transition from 1.8 V to 13.8 V.

ABSTRACT. Probabilistic behavior of logic gates represents one of the main reliability problems associated to CMOS circuits supplied at very low supply voltages. This paper aims to analyze the impact of probabilistic faults in interconnects, by means of HDL saboteur-based simulated fault injection (SFI). We propose four types of saboteurs: the simplistic probabilistic type, a switching type - aware and two data dependent types. We have analyzed the behavior of the Wishbone bus in the presence of probabilistic errors. Several sets of simulations have been performed, by injecting probabilistic faults on address, control signals and data components of the bus. The performed simulations indicate that the simulation time for a SFI campaign is 1.8x higher with respect to the gold circuit.

ABSTRACT. Embedded systems support more and more features. Authentication and confidentiality are part of them. These systems have limitations that put the public-key RSA algorithm at a disadvantage: Elliptic curve cryptography (ECC) becomes more attractive because it requires less energy and less area. A lot of attacks exploit physical access on cryptographic hardware device: power analysis attacks (SPA, DPA), or timing analysis attacks. The coprocessor presented here supports all critical operations of an ECC cryptosystem and has been secured against side channel attacks.

ABSTRACT. This paper presents the design of an ASIC for the task of multi-speaker phoneme recognition in continuous speech environments. The phoneme recogniser is based on DWTs for feature extraction and the One-against-one SVM method, along a priorities scheme, for classification. The ASIC design was fabricated on an AMS 0.35μ CMOS C35B4C3 chip. The final ASIC design resulted into a chip size equal to 43.35mm2, with the requirement of an external memory storage of size 18.25Mb. Moreover, the ASIC design of the phoneme recogniser is approximately 4 times faster than the equivalent software-based approach and consumes 12.5mW, making it appealing to mobile devices. The performance results obtained from the ASIC design confirmed that this system is a promising basis for future hardware ASR systems.

ABSTRACT. A tunable millimetre-wave generator using optical phase modulators with no DC bias and no filters (neither RF nor optical filters) is proposed in this paper. A 60 GHz RF signal is optically generated by multiplying the frequency of an input RF signal at 7.5 GHz by a factor of 8. The electrical suppression ratio is around 50 dB as shown by simulations.

ABSTRACT. In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13$\mu$m SiGe BiCMOS technology and a threshold tunable between $\pm$160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a datarate of up to 80Gbps can be achieved.

ABSTRACT. A 60 GHz down-conversion mixer used in the unlicensed 60 GHz band system in 65-nm CMOS technology is presented in this paper. Based on the double-balanced Gilbert cell, the mixer comprises a cross-coupled pair to rise conversion gain and two series LCR network resonating at IF frequency to enhance bandwidth. As a result, both high gain and broad bandwidth are achieved. From the simulation results, the conversion gain exceeds 10 dB and 3-dB IF bandwidth is from 8 GHz to 16 GHz, the OP1dB is –6 dBm and noise figure is below 12 dB at the interesting band. The mixer consumes 5 mA from a 1.2 V supply without buffer, and the chip area is 1×0.75 mm2 with pads.

ABSTRACT. This paper presents a high conversion gain doubler-balanced active frequency doubler for millimeter-wave application. The frequency doubler contains an improved push-push structure, two quarter-wavelength transmission lines, and output power enhancement using negative resistor. The 3-dB band of the frequency doubler is 19~28 GHz of input frequency, the maximum conversion gain reaches –5.3 dB, the fundamental rejection is above 55 dB, and the power consumption is 17 mW under 1.2V VDD. The frequency doubler is designed in 65nm CMOS process.

ABSTRACT. This article presents a fractional-N phase-locked loop (PLL) for the use in frequency-modulated continuous wave (FMCW) radar systems. The presented design supports division ratios from 59 to 4092 with a maximum input frequency of 7 GHz, covering the 2.39 GHz to 3.28 GHz and 4.79 GHz to 6.55 GHz bands using a dual-band voltage-controlled oscillator (VCO) with a frequency resolution of 0.6 Hz. This corresponds to a large relative bandwidth of more than 31 %. Reference spur levels are lower than −65 dBc while phase noise is at −103 dBc/Hz at 1MHz offset frequency. A key feature for radar applications is the automatic chirp waveform generation. The complete circuit including VCO consumes less than 122 mW and is implemented using an IBM 180 nm SiGe BiCMOS process.

ABSTRACT. Abstract—An integrated 5.5 GHz low power voltage-controlled oscillator (VCO) has been designed and implemented in a 250 nm CMOS process. This cross-coupled LC VCO achieves measured phase noise of about 90 dBc/Hz at an offset frequency of 1MHz and a power consumption of less than 2.1 mW. The output frequency of the VCO can be tuned from 5.19 GHz to 6.12 GHz, which correspond to a 16.9% tuning range, obtained by tuning the control voltage of the varactor. The VCO output power remains nearly constant over the entire tuning range.

ABSTRACT. This paper reports comparative analyses of phase noise in common-source cross-coupled differential pair, differential Colpitts, Hartley and Armstrong LC oscillator topologies designed in 28 nm CMOS technology for 10 GHz operations. The Impulse Sensitivity Function is used to carry out qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each topology. The analyses show that the lowest phase noise is exhibited by the differential Armstrong topology. Additionally, the results show the impact of flicker noise on phase noise performances.

ABSTRACT. The operation of a periodically switched cross-coupled oscillator is considered in this work. First, it is shown that this architecture corresponds to a Van der Pol oscillator. Based on that, a novel analytical solution is proposed for the Van der Pol equation taking into account the time-dependent amplitude and frequency variation at the starting of oscillation. In addition, an original specific model for the pulsed oscillations is presented. Comparison with numerical simulations of the Van der Pol equation shows very good accuracy.

ABSTRACT. A current feedback instrumentation amplifier (CFIA) with extended common mode input voltage range is presented. Referred to input offset of 70𝜇V is obtained firstly by using chopping and gain enhancement techniques in order to increase the DC gain and secondly by adding an offset reduction loop (ORL). The proposed circuit is implemented in a high voltage 0.5𝜇m SOI technology. A common mode rejection ratio (CMRR) of 260dB has been obtained by using single ended three stage architecture with a common mode input voltage from -18V to 80V. The stability of the CFIA is ensured for a close loop gain of 20V/V.

ABSTRACT. In the race to deliver ever smaller and faster devices, bulk FinFETs are seen as a viable alternative to planar bulk technologies. With that in mind, a new benchmarking scheme is implemented in order to effectively and fairly compare, in simulation, a 10nm FinFET technology with a 28nm planar CMOS one on a 100 MHz gain-bandwidth operational amplifier. For identical phase margins, the 10nm design consumes 99 μA compared to over 123 μA in 28nm, yielding a substantial decrease in power consumption in favor of the FinFET-based design.

ABSTRACT. This paper presents a fully-differential currentfeedback instrumentation amplifier with rail-to-rail input common-mode (CM) voltage range. Gm mismatches due to input CM variations have been reduced exploiting an original commonmodes equalization loop. Chopping modulation is adopted to improve the performances of the amplifier in terms of offset and low frequency noise, while the intrinsic low-pass transfer function of the amplifier is exploited for the reduction of the offset-ripple. A prototype has been designed using the UMC 0.18um MM/RF CMOS process. Simulations, performed with a supply voltage of 1.5 V, showed that a maximum relative gain error of nearly ±1.5 %, against rail-to-rail input CM voltage variations, can be achieved

ABSTRACT. In this paper, we presented a prototype of a bootstrap transimpedance amplifier for high speed optical transcutaneous wireless communication. Utilizing the bootstrapping technique, the achievable receiver bandwidth has been significantly increased. The conventional TIA and proposed BTA were fabricated and tested. The BTA achieves a transimpedance gain of 1.2 k (61.5 dBohm) over a 3-dB bandwidth of 61 MHz in the presence of an input an input capacitance of 350 pF. The proposed BTA enables designers to use large-size the photodiodes, increasing the transmission efficiency of the TOTL system, which in turn allows for a reduction of the transmit power in the implantable transmitter.

ABSTRACT. A high accuracy current sense amplifier with input common mode range extending beyond the positive supply rail is presented. The offset voltage is minimized using an auto-zero topology with a fully differential internal path. Characteristics of the presented amplifier include an input voltage range of 30V, independent of the supply rail, a fixed gain with a typical gain error of 0.05% and a referred-to-input offset voltage of less than 10μV in the −40°C to 125°C temperature range. The proposed architecture was implemented in a 0.5μm CMOS process and its performances were confirmed by post-layout simulation results.