PROGRAM FOR TUESDAY, JULY 1ST

ABSTRACT. This paper presents a behavioural model suitable for the simulation of low-power Sigma-Delta Modulators. Second-order effects affecting the settling behaviour of the switched-capacitor integrator was included, leading to improved accuracy. Due to the oversampling mode of the converter, transistor-level simulations are extremely time consuming. Accurate behavioural models are thus mandatory in the first design phase of the modulator, in particular when the involved analog blocks must be optimized for minimum power consumption at a some converter resolution.

ABSTRACT. The Electronic System Level design flow aims to manage the great complexity of today’s Systems-on-Chips: design and verification methodologies start from abstraction levels higher than RTL(Register Transfer Level), referred to as Transaction Level Modeling(TLM). Assertion-based Verification(ABV), a widely adopted verification technique for RTL design, started to prove its efficiency at TLM. Actually, there is a real need for a complete verification flow covering all the design flow to reduce the growing verification effort. In this paper, we describe the implementation of an approach for temporal assertions refinement from TLM to RTL, using a set of transformation rules. The reuse of TLM assertions is the basis of the ABV flow. Our approach is experimented on an industrial use case.

ABSTRACT. The proposed ADC is formed by a second-order multibit noise-shaping converter using a time domain integrating quantizer as first stage and a Differential Gated-Ring Oscillator as second stage of the multistage architecture (MASH). The first-order noise shaping behavior of the DGRO allows to obtain a total third order noise shaping performance in the final ADC output. Moreover, using the arrangement proposed in this work, the low power requirements demanded in biopotential read-out circuits can be achieved. This because the multi-bit flash quantizer used in standard noise-shaping ADCs has been replaced by a time domain integrating quantizer that uses a one bit comparator and a PWM DAC.

ABSTRACT. A second order CT Σ∆ modulator for audio frequency sensory systems in 180µm TSMC CMOS process is presented. The overall power consumption is distributed evenly among segments of the loop to attain adequate number of bits without the need to sacrifice power. The design incorporates a C-gm based current mode structure with 2nd order noise shaping, a 25 kHz bandwidth, a sampling frequency of 12.8 MHz marking an OSR of 256 and a total power consumption of 4.3µW. Consequently the proposed loop achieves a FOM of 1fJ/conv.

ABSTRACT. Continuous time digital filtering offers the possibility of implementing low power, tunable, low frequency filters required for interferer rejection in ultra low power radios. The bottleneck of such architectures lies in the limited linearity of the continuous time analog to digital conversion (CT-ADC) stage. This paper presents an interferer resistant wake-up radio architecture based on continuous time digital filters and discusses different ways of improving the linearity of the analog to digital conversion stage without sacrificing its power consumption.

ABSTRACT. In the context of green communications, millimeter wave bands are investigated to ensure mobile access and backhauling. Such transmissions can be performed with the IEEE 802.11 Directional Multi-Gigabit (DMG) modes, designed for very high throughput in the 60 GHz band. However, the DMG Orthogonal Frequency-Division Multiplexing (OFDM) physical (PHY) layer specifications corresponding to the highest data rates are not energy-efficient. Therefore, in this article, we propose easily implementable green improvements for IEEE 802.11 DMG OFDM PHY: a change of error correcting code and a new modulation and coding scheme. Binary error rate performance evaluations are made to show the green benefits of our improvements.

ABSTRACT. Electrical energy systems (EESs) represent a wide class of systems involving consumption, generation, distribution and storage of energy. Examples of such systems can be found at various scales, ranging from smart systems-on-chip to smart grids. The conventional design methodology uses the model-based approach provided by commercial platforms such as Matlab/Simulink, and relying on built-in model libraries. This paper presents a modeling and simulation methodology for EESs based on the SystemC standard (and its Analog and Mixed-Signal extension SystemC-AMS). Simulations show that the proposed approach provides accuracy comparable to Matlab/Simulink results, with higher modularity and an average speedup of 36x.

ABSTRACT. Signal and Power Integrity analyses assume a paramount importance to ensure a secure integration of high-speed communication interfaces in low-cost highly-integrated System-in-Package(s) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess/optimize system functionality. Ensuring post-silicon correlation, electrical macromodels of Package/PCB parasitics and I/Os are generated and included in the testbenches to expedite simulations. Using as example an LPDDR2 interface in a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation runtime speedup, and enable interface-level studies of Package/PCB parasitics effects on signals/PDNs and timing-budget degradation.

ABSTRACT. With the current hardware potentiality, it’s unavoidable to make use of simulation tools to develop, improve and optimize the designed networks. Many network simulators are available, but they mainly concentrate on the protocol aspects of the design, i.e. they work on a very high level of abstraction. Rather, in many applications it may be useful, important or even critical to observe and manage at the same time high-level and low-level parameters like the power in the channel or the packet loss. In this paper we present a Bluetooth network simulator that let the user to work both on application level and on link management level. The Bluetooth simulator has been implemented using SystemC and it has been developed with the aim of modeling a real microcontroller-based device.

ABSTRACT. In this paper we present a new algorithm, based on Kirchhoff's Current Law (KCL) verification, for assessing convergence in circuit-level simulation and its implementation in the NGSPICE open source circuit simulator. We start from the analysis of false convergence problems appeared in the analysis of test circuits that we found to be related to the convergence checks that NGSPICE simulator inherits from SPICE3F5. These check are inaccurate in some cases, so we propose to replace them with a new, efficient, algorithm based on KCL verification. The methodology to verify KCL of the circuit is detailed in this paper, along with the extraction flow, required to compute every KCL contribution.

ABSTRACT. A step-by-step simulation methodology for large-bandwidth Track-and-hold (T/H) microwave circuit is proposed. A T/H circuit is characterized accurately under the Cadence environment. With the consideration of a specific windowing function, linearity simulation analysis could be done effectively. Moreover, the use of an input frequency generation function, in accordance with theoretical calculation, allow to treat the entire input bandwidth (BW). A simulated switched emitter follower (SEF) structure with 32GHz effective bandwidth and a 4G/S clock illustrates our methodology.

ABSTRACT. A four-path time interleaved current steering DAC is presented. It requires the same number of unity current generators of the plain counterpart, thanks to the use of a digital Sigma-Delta modulator, thus leading to a lower number of unity current switchings. The benefit is that the non-linearity caused by clock feedthrough is attenuated. Behavioral level simulation results show that the SFDR of a 12-bit DAC operating at 12 GS/s can be 60 dB.

ABSTRACT. In this paper a fully differential current conveyor based switched capacitor (SC) integrator is presented. To operate the current conveyor (CCII) integrator with high linearity, calibration is used to correct for its non idealities. Simulation results are presented to show the effectiveness of the calibration technique. The presented integrator is applied to design of a 2nd order Delta Sigma ADC. A comparison of the calibrated and uncalibrated ADC outputs reveals that the calibration technique improves the dynamic range and SNDR significantly. The oversampled ADC gives more than 85 dB DR and 76 dB SNDR for bandwidth of 0.5 MHz and clock frequency of 80 MHz respectively.

ABSTRACT. The bootstrap technique is known to increase the linearity of Sample and Hold (S/H) circuit by reducing the input signal dependency of the transistor-switch resistance. But some nonlinearities remain due to parasitic capacitances, mobility degradation and back gate effect resulting in a second order harmonic spurious which can be reduced with a differential architecture. However mismatch between channels limits this technique. In this paper, we provide a general framework to analyze the residual nonlinearity in bootstrapped S/H. Statistical laws are also provided converting harmonic distortion specifications into matching requirements for differential sampling and therefore provide key rules for S/H designers.

ABSTRACT. A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range.

ABSTRACT. This paper presents a high-speed serial interface with a PLL-less clock and data recovery circuit. A digitally controlled delay line combined with a sample&hold register is used as self-calibrating time-to-digital converter measuring the phase offset between data and clock. The same line is then utilized to delay the clock appropriately to allow errorfree sampling of the data. In contrast to analog DLLs, initial lock can be achieved after transmission of four bits requiring minimal protocol overhead for synchronization in burst-mode transmissions. The CDR circuit is optimized for 1.228Gbit/s and consumes 1.9mA from 1.2V supply, with a maximum jitter of 1.8ps. The overall power consumption is 10.7mW.

ABSTRACT. We present a novel low-cost built-in test approach for the Error Vector Magnitude (EVM) performance of RF transceivers. We rely on built-in sensors to extract low-cost measurements that can be used thereafter to predict implicitly the EVM. The key attribute of the sensors is that they are non-intrusive, that is, they are not electrically connected to the RF transceiver. Hence, the proposed built-in test approach does not necessitate any design modifications in the RF transceiver. The sensors provide measurements that track process variations and thereby they can predict drifts in the EVM value that are due to such process variations. Simulation results demonstrate that the proposed built-in test predicts the EVM with less than 6% error.

ABSTRACT. This paper presents two implementations of the fast Fourier transform decomposed into vector operations. This approach is appropriate for cases where the data to be transformed is stored in an unorthodox order, well suited for radar and sonar data processing. The described procedures performing a vector FFT were implemented for TigerSHARC DSP and NVIDIA CUDA platforms. Their performance was measured and compared with highly optimized library procedures.

ABSTRACT. A new Power Line Communication (PLC) solution over a DC powerline is presented for remote management of batteries. This solution rely on the well known Controller Area Network (CAN) protocol and is designed to be directly compatible with existing CAN controllers. The presented PLC-CAN system is a low complexity and low cost solution suitable for short and low power DC bus used in small scale autonomous systems. Simulations of the communication channel over the frequency range [0.5 - 10] MHz are conducted to validate the concept’s feasibility. Experimental measurements on prototypes are then presented and show achievable data rates of 116 kbit/s.

ABSTRACT. We present high-performance temperature sensors utilizing spray deposited carbon nanotube (CNT) films as the active sensing material. To evaluate device performance, the change in device resistance with respect to change in temperature is monitored. The fabricated sensors show very good electrical response to change in temperature. Also a comparative experiment is carried out to investigate the effect of CNT film thickness on the sensor characteristics. Results show that films with higher thickness exhibit a lower temperature coefficient of resistance compared to those with lower thickness, while demonstrating higher stability and reproducibility. Finally, another important feature of devices presented is that the change in resistances with respect to temperature change is nearly linear.

ABSTRACT. Porous Silicon Nanowires represent promising electronic devices with a range of applications exploiting the irregular microscopic structure of PS. Variability of its electrical properties with technological process makes computer simulation of PS-NWs cumbersome. We present a model of PS-NWs which can be implemented in physics-based software TCAD Atlas thus contributing to the investigation of the effects of the structure on the material resistivity. Simulations have been performed on PS-Nws with characteristics deduced from our fabricated devices. We analysed the dependence of current from applied voltage and doping in relation with the electric field and carriers' mobility. An electrical model for PS-NWs is suggested for implementation in commercial circuit simulators (Eldo in this case).

ABSTRACT. This paper presents a four-folded current-mode vertical Hall device. The current spinning technique is applied to a vertical Hall sensor driven in current mode to eliminate the offset and to increase the sensitivity. Different geometries have been studied and simulated by using a simulator based on finite element method. A four-folded three contacts vertical Hall device model displayed the lowest residual offset and the best sensitivity. Simulations results, obtained in two dierent environments, are compared and discussed. COMSOL results are validated with respect to the electrical behavior of an 8-resistor Verilog-A model implemented in Cadence environment. Simulations show that the achieved sensitivity can be better than 160 mT(^-1), a remarkable performance for vertical Hall sensors.

ABSTRACT. The present work describes the design, fabrication and experimental results of a 3-terminal laterally actuated tungsten nano-electromechanical (NEM) relay which is monolithically integrated in a 0.35$\mu$m commercial standard CMOS technology. The movable structure is released by means of a simple one-step maskless wet etching. The switch shows an abrupt switching with less than 5 mV/decade and a good on-off current ratio of $\sim 10^4$ although it exhibits an on-state contact resistance $R_{ON}$ around 500 M$\Omega$. Also, the relay is cycled up to 1500 times in ambient conditions showing great endurance but variability in its contact.

ABSTRACT. This paper presents a full-custom tunable gain transimpedance amplifier (TIA) designed to work as a sustaining amplifier for a monolithic CMOS-MEMS oscillator. Based on a capacitive detection of the MEMS current, the implemented differential structure allows to compensate a wide range of motional resistances (between 1.4MΩ to 20MΩ) exhibiting an exceptional low input current noise of 32fA/√Hz @ 20 MHz.

ABSTRACT. With the continuous downscaling of CMOS technology over the last two decades, reliability of CMOS circuits has become a more critical design issue due to the worsening effects of process variations. Therefore, increased variation and mismatch problems have enforced designers to consider robustness as a design objective. Besides the variability problem, increased non-idealities with more advanced technologies have complicated circuit analysis, and caused unacceptably long design times. Therefore, design automation tools for analog circuits have become crucial to keep the synthesis time within acceptable limits even if variability analysis is included. In this paper, two different methodologies are proposed for variation aware design automation of analog circuits.

ABSTRACT. Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentration discontinuity of these contact regions can have a big impact on parasitic diffusion currents of minority carriers. This work gives a description of these effects by device physical simulations of PN junctions under different injection levels of minority carriers. The perturbation of boundary conditions for electrons diffusion is also studied inside the substrate bulk in case a highly-doped substrate is used for high-voltage technologies.

ABSTRACT. As part of our ongoing research, we describe an algorithm based on probability analysis and logic principles for computing the impact of gate failures on the circuit output. We also propose a Bound and Propagate based methodology to handle the reconvergent fanout issue. A reliability evaluator has been developed around the open source logic synthesis tool ’abc’ to allow for the integration and evaluation of our method in the context of an IC design flow. This approach had tremendously reduced the computation time while maintaining adequate precision. Simulation results for several benchmark circuits demonstrate the accuracy and the simulation time advantages when compared to MonteCarlo simulations.

ABSTRACT. A low start up voltage DC–DC converter for thermoelectric energy harvesting is presented in this paper. Output voltage of a thermoelectric energy generator (TEG) provides an output voltage from 40mV to 400mV, depending of thermal gradient. In order to increase input voltage, a boost converter is used. The proposed DC–DC converter is composed of two main sections. One provides a high duty cycle pulse width modulation (PWM) for a forward control. It is used when the voltage coming from the TEG, is in the 40mV to 150mV range. As the TEG voltage it is higher than 150mV, a feedback circuit is switched on. It provides a more accurate control of the output voltage. Entire DC–DC converter is implemented in a 65nm bulk CMOS technology.

ABSTRACT. Abstract—This document presents an alternative antenna matching strategy for RF Harvesting circuits, based on the use of wire-bonds as external matching inductors. In the following, the electrical characteristics of the bond-wires are evaluated in terms of inductance, quality factor and UHF behavior. Pad deembedding techniques are applied to reduce parasitic influence. A HFSS model is built as well in order to provide a predictive tool for further improvements. The measurements and simulations are compared and a real-case application is presented.

ABSTRACT. This paper analyzes the working principle and structure strength of vertically integrated piezoelectric nanowires into active devices for sensing or energy harvesting applications. Finite element method simulations have been used to evaluate the performances of the devices working in flexion and compression modes under varying input pressure. The geometric influence on the energy generation is also analyzed.

ABSTRACT. This paper describes design of the wireless sensor network (WSN) node for distributed active vibration control system for the automotive application. The node using one piezoelectric element provides several features (sensing, shunting and energy harvesting). Implementation of the WSN node with designed SSHI circuit is presented, obtained results are described.

ABSTRACT. Interest in RF energy harvesting (EH) systems as green and renewable energy schemes has increased remarkably in recent years thanks to their unlimited applications. The key element on the receiving side of a EH system is the rectenna which receives electromagnetic power and converts it into electric power. To reduce the size of the rectenna, it has been suggested to combine antenna and filter (filtenna). This paper presents a dual-band filtenna to harvest RF energy from cellular network. By using the Printed-IFAs with a slot on the ground plane, the high-order harmonics are rejected. The measured antenna return loss over 2– 8GHz is less than 1.5dB so all the high-order harmonics are suppressed. The realized gains of the antenna are 1.9dBi at 900MHz and 2.55dBi at 1800MHz band.

ABSTRACT. This article presents a power detector proposed for low-cost millimeter-wave applications. The detector uses MOSFET transistor in sub-threshold region in order to realize the signal rectification benefiting from the natural exponential characteristics of MOS transistor in this regime. The detector was designed using the BiCMOS 55 nm technology from STMicroelectronics and compared counterpart. Theoretical analysis and simulation results demonstrate the advantage of MOS detector in terms of input impedance which reduces the impact of the detector on the device under test (DUT). However, the bipolar transistor provides faster responses due to its higher current capability.

ABSTRACT. An enhancement of an analytical algorithm to simplify and structure the design of stacked power amplifiers is presented in this work. This enhancement includes the calculation of passive networks, which compensate the parasitic capacitances of the transistors and thereby increase the distortion-free output power and the power added efficiency (PAE). As an example the algorithm is applied to a power amplifier (PA), using the IBM 180 nm CMOS process. The PA operates at 2GHz for the long term evolution (LTE) standard. The post-layout-simulation exhibits an output power in the 1 dB compression point of 28.2dBm, leading to a PAE of 30%. The PA fulfills the specifications of LTE and therewith the high requirements on linearity.

ABSTRACT. This paper presents the design of a mm-Wave PA for a transmitter of an E-Band mobile backhaul network, implemented using a 55nm SiGE BiCMOS technology. It has a 4- stage balanced CE configuration and the outputs are converted to single-ended using an integrated balun, which provides insertion losses smaller than 1dB at E-Band frequencies. The PA presents a maximum S21 of 15.5 dB at 74GHz and its 3-dB bandwidth covers from 66 to 87 GHz. Its output 1-dB compression point has a maximum of 20dBm and is above 18.75dBm across the whole E-Band, with a peak PAE of 35%. The different stages are externally biased and the Vcc voltage is 1.5V. The total DC power consumption is 275 mW.

ABSTRACT. In this paper, a linear model for intrinsic power and efficiency in Radio-Frequency Switched-Capacitor Power Amplifiers (SCPA) is presented. Given a target output power and frequency of operation this model enables sizing the output stage inverter for maximum efficiency by means of back-of-the-envelope equations. The model is validated by SpectreRF simulations for a low-power CMOS 28nm technology for different frequencies of interest.

ABSTRACT. In this paper a high gain, high power output stage designed in a 250nm SiGe BiCMOS technology is presented. The used topology together with a discussion on the stability of the output stage is explained in detail. In order to increase the gain of the output stage and thus increases the attainable power added efficiency (PAE), positive feedback is used. Furthermore a formula predicting the input impedance of a common base transistor at high frequencies is deducted which explains and predicts the magnitude of the feedback mechanism. The output stage achieves a peak gain of 14.4dB at 31GHz with a maximum output power of 22dBm.

ABSTRACT. In this work, a base-station design is proposed for passive UHF RFID tags that use pulse-width modulation (PWM) in backscattering communication. The theoretical analysis of the PWM backscattering is presented along with the challenges it creates in the base-station design. The self-jamming issue in the base station is analyzed with a numerical case study. The theoretical analysis of the reverse communication channel is made. A method is proposed for wired backscattering measurements, which models the path loss and reflection from the tag eliminating the need for wireless measurements in an anechoic chamber. It is shown by measurements that the base-station is capable of measuring the pulse-width of the backscattered signal with an error less than 1% at a distance of 2 meters.

ABSTRACT. We present an innovative sensor chip, exploiting backside illumination of a silicon-on-insulator (SOI) wafer containing custom single photon avalanche diodes (SPADs), flipped and wafer-bonded on a standard CMOS wafer integrating the analog front-end circuit, in-pixel digital processing and readout electronics. Two major improvements are achieved: higher pixel density and fill-factor, since these detectors are placed on the top of the corresponding smart-pixel electronics, instead of being placed side-by-side (as in planar structures); enhanced spectral sensitivity in the near-infrared, up to 1 µm wavelength, thanks to thicker active volume within the SOI detector wafer and to the backside illumination of the active area.

ABSTRACT. CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are trade- offs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the implementation of image sensors. A set of 5x5 matrices of SPADs with different sizes and shapes is designed to study the relationships between FF, crosstalk and DCR, and conceive an accurate behavioural model of SPAD arrays. The testchip is fully operative and preliminary experimental results are presented.

ABSTRACT. This paper describes how thin films (thickness ~1-2μm) of highly loaded magnetic nanocomposites can be obtained by encapsulating metallic magnetic nanoparticles (diameter ~30nm) inside a polymer matrix. Films are further characterized in order to check their capability to be used in RF applications.

ABSTRACT. This work focuses on the design and manufacture of electrochemical metallization memory cells (ECM) also called CBRAM (Conductive Bridge RAM). Memories stacks were fabricated by sputtering on a SiO2/Si substrate and are characterized by near-field microscopy and mercury drop probe. Stacks used a layer of Ge2Sb2Te5 (GST) as a solid electrolyte. The measurements prove the resistance switching of the stacks due to the formation/dissolution of metal filaments in the GST layer. However, the memory devices do not show a switching behavior but an ohmic behavior. This result is interpreted through physical analysis showing the presence of silver in all layers of the memory devices. Finally, a physical model is presented. This model was used to fit the experimental curves.

ABSTRACT. A nanonet (NANOstructured NETwork) is an original structure that exploits the unique properties of nanowires (NW) such as high surface area and large aspect ratio while avoiding the complex and expensive processing required for individual NW devices. In this work, the vacuum filtration method is used to elaborate homogeneous, reproducible and conducting silicon nanonets. A study of their morphological and electrical behavior is provided as a function of the SiNW length and density. We demonstrate that despite the complexity of the nanonet geometry, it is possible to control their morphological and electrical properties that strongly depend on the SiNW length and density. In view of the obtained properties, we predict the great potential of Si nanonet for a wide range of applications.

ABSTRACT. We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features – termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4X increase in ‘ON’ current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar ‘OFF’ current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption.

ABSTRACT. In emerging multi e-beams exposure tools, the release of hydrocarbonaceous species by resists outgassing is unavoidable and leads to premature contamination of optics systems. In this work, we present an experimental methodology allowing the investigation of the specific silicon micromachined membranes (called mimics) carbonaceous contamination induced by resist outgassing under e-beam radiation by using a dedicated experimental setup designed in CEA-Leti. The FIB-SEM and XPS characterization techniques were used to determine the contamination layer thickness and elementary composition, respectively. A first process-oriented conclusion from this work shows that the contamination layer growth depends on e-beam current density and hydrocarbon pressure in the vicinity of the mimics.