PROGRAM FOR THURSDAY, JULY 3RD

ABSTRACT. FPGA undergoes a large number of test configurations for faults detection and diagnosis which requires a significant amount of test time and off-chip memory to store test configuration bits. Some FPGAs support partial reconfiguration in which a portion of FPGA can be reconfigured without reconfiguring the remaining portions. This partial reconfiguration approach can be utilized for FPGA testing, to reduce the amount of test time and configuration bit storage. In this paper, we propose a Built-In Self-test (BIST) scheme utilizing partial reconfigurability of a mesh FPGA. To implement the BIST scheme, automated tools are developed to produce the required configuration bitstream using standard FPGA CAD flow.

ABSTRACT. Modern cars are no longer mere mechanical devices and they are dominated by a large number of IT systems that guide a wide number of embedded systems called ECU. While this transformation has driven major advancements in efficiency and safety, it has also introduced a range of new potential risks. After a brief introduction of the security in automotive environment we investigate how the automotive community approached this problem. In order to ensure some security aspects in automotive environment, it is needed a hardware implementation of the AES algorithm with higher speed throughput than existing solutions. For this purpose, a new hardware implementation of this cryptographic algorithm is presented.

ABSTRACT. The XG-PON standard for Passive Optical Networks (PONs) has imposed requirements for high performance processing in the architectures of network equipment. Especially, the 10Gbps receiver designs of the terminals and the network units (ONTs and ONUs) become quite demanding. The current paper focuses on the XG-PON ONT/ONU receiver and presents a FPGA design realizing the decoding functions of the XG-PON physical adaptation layer: The scrambling, the RS(248,216) decoding and the Hybrid Error Correction (HEC) architectures, which are designed to communicate through a 64-bit bus. This work describes the components' features and validates the results by showing the design's performance on FPGA Xilinx Kintex 7.

ABSTRACT. Many applications impose safety and/or security constraints which require protections against the effects of transient faults.In embedded microprocessor-based systems the system dependability is strongly correlated with internal register criticality since external memories are protected by error correcting codes.The robustness analysis of these systems consists in precisely assessing the criticality of internal registers used by the application program.This paper presents an approach based on modeling the effect of transient faults taking into account the micro-architectural features and proposes a new methodology to refine and accelerate evaluations of register criticality.This new approach is compared with fault injections.The results show the effectiveness of the prediction algorithm.

ABSTRACT. A DC-link voltage equalization algorithm (DCL-E) for Three-Level Neutral-Point Clamped converters (NPCs) is proposed in this paper. It consists of appropriately regulate DC-link currents with the aim of equalizing DC-link voltages as fast as possible, minimizing capacitor voltage and current ripple and prioritizing NPC load requirements at the same time. This goal is achieved by means of suitable PWM patterns, which also guarantee an appropriate DC-link capacitor exploitation over both transient and steady state operation. The effectiveness of the proposed DCL-E is verified through a simulation study, which refers to the case of a three-phase NPC that feeds a Surface-Mounted Permanent Magnet Synchronous Machine.

ABSTRACT. This paper presents an overview of the switching noise analysis in a DCDC converter by considering the first order parasitic elements involved in the noise generation. Simplified theory is provided in order to help circuit designers selecting the optimum components for low noise operation. Theory versus simulation and measurement are carried out.

ABSTRACT. In this work we quantify the figures of merit of p-n junction based adiabatic graphene circuits implemented through a new logic design style, the Adiabatic Pass-XNOR Logic style (Adiabatic-PXL). We first show how graphene p-n junctions naturally implement transmission gates with embedded XNOR functionality (the Pass-XNOR gate); second, we present a dedicated logic synthesis flow for integrating those gates into adiabatic logic circuits with ultra low-power features. Simulation results have shown that Adiabatic-PXL circuits are 4.2X to 5.5X more energy efficient than non-adiabatic counterparts, still with significant amount of area savings (67\% less devices on average).

ABSTRACT. A novel numerical 3D-model for simulations of random networks of carbon nanotubes is presented. This new algorithm takes into account the real 3D nature of these networks, allowing a better understanding of their electrical properties. CNTs are modeled as stiff cylinder with geometrical properties derived accordingly to different distributions. In this model CNT are allowed to bend in order to adapt in a realistic fashion to the surrounding environment. The electrical behavior of the network is simulated with a SPICE program. A temperature analysis has been performed, showing a good match between the simulations and the experiments. The present approach constitute the basic building block for the simulation of a variety of sensors on rigid and flexible substrates.

ABSTRACT. Among emerging technologies, Quantum dot Cellular Automata (QCA) is one of the most studied because it suffers very low power consumption and it combines logic and memory on a unique device. The behavior of circuits is therefore largely affected by defects and fabrication variations. In this work we present an innovative test environment for NML technology. The test algorithm is integrated in ToPoliNano, our design and simulation tool for emerging technologies. this tool it is possible to design and test complex NML circuits considering the effect of process variations in terms of Yield and Output Error Rate. The approach gives then feedback to the technologists, remarkably helping the future development of this technology.

ABSTRACT. In this paper, a compact model for PCM cells, which evaluates the state of the cell during and after a programming operation, is described. The model can simulate the state of the GST during the whole programming operation. It can also simulate the dynamic of the amorphous cap growth during a RESET operation, as well as the crystallization process, expressed in terms of Crystal Fraction (CF) during a SET operation. The model was validated through comparison with experimental data.

ABSTRACT. A current-mode delta-sigma modulator is presented utilizing a Current Conveyor and a Current Controlled Oscillator (CCO). Second order noise shaping is achieved although a very simple topology is used with only one integrator. The impact of oscillator non-linearity is kept low thanks to a pseudo-differential design. Simulations predict an SNDR of 102 dB at 10 kHz bandwidth, 5 MHz sampling frequency, oversampling ratio of 256, and a CCO non-linearity of 1%. Even at 5% oscillator non-linearity an SNDR of 72 dB is achieved. A feasibility check is accomplished by designing the proposed topology on transistor-level.

ABSTRACT. The ADC here proposed is part of a larger VLSI (Very Large Scale Integration) circuit, called Detector Control Unit (DCU), whose aim is to monitor some critical quantities of the CMS (Compact Muon Solenoid) central tracker, inside the Large Hadron Collider (LHC). The damages caused by radiation in such an environment are monitored to provide real time information about the electrical/physical scenario of detectors. This allows to increase performance and life-time of microelectronic circuits. The 32 channels Wilkinson ADC has been designed in CMOS 65nm technology and it has a resolution of 12 bits. A definitive 11 bit accuracy has been obtained. Its power consumption is about 500uW and operates with a 40 MHz clock frequency. The signal sample rate is about 5.5kHz.

ABSTRACT. In this paper a calibratable CR SAR ADC is implemented with a unit capacitance of 1.54fF which is much smaller than the capacitance used in most novel SAR ADCs. As a result, the area and the power consumption are reduced significantly. In the targeted 65-nm technology with a supply voltage of 1.2V, an FOM of about 2.76fJ/conversion-step is expected as it is achieved through simulations. Since the larger mismatch between such small capacitors of the ADC degrades its linearity significantly, a foreground calibration technique based on trimming each capacitance with smaller switchable capacitors is developed to compensate the mismatch. Also, for the purpose of mismatch detection, an offset-calibratable double-tail latch comparator is designed to achieve an offset below 70μV.

ABSTRACT. This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is applied which reduces the total input capacitance by 50%.

For a low-frequency input signal, measured SNDR and SFDR of the presented SAR ADC are 48.7 dB and 57.8 dB. The effective resolution bandwidth (ERBW) is 19 MHz. The ADC draws 17.4 mA from a 2.6 V supply.

A formula for relating static nonlinearity (INL) measurements with dynamic SNDR/ENOB measurements is derived. From an INL measurement, the impact of nonlinearity and noise on SNDR and ENOB is derived.

ABSTRACT. A new architecture for differential bandgap voltage references is presented. The system is based on a switched capacitor amplifier that perform correlated double sampling to cancel offset and reduce flicker while maintaining a valid output voltage throughout the clock cycle. The circuit noise is filtered by an intrinsic, discrete time low pass function with tunable cut-off frequency. A prototype designed with 0.18 um CMOS process is described. Preliminary performances are estimated by means of periodic noise analysis carried out with the SpectreRF simulator.

ABSTRACT. This paper presents a BandGap reference circuit with low sensitivity to temperature and to the voltage supply variations. It has been designed to be Radiation-Hard up to 1GRad. It has been developed in a commercial 65nm CMOS technology with 1.2V of nominal voltage supply. A current-mode architecture has been chosen to allow the low-voltage operation. Particular attention has been dedicated to circuit radiation hardness, in order to provide a stable voltage signal also with high radiation levels. The BandGap reference has been tested with temperature range from -10°C to 50°C. The output value is around 330 mV with an error of 0.06% in nominal conditions. The maximum output deviation in the worst case is about 3.5%. The noise is about 180uV and the power consumption is 240uW.

ABSTRACT. In this work, a current reference circuit is proposed using 0.18 um standard CMOS technology and the simulations were performed using the Cadence Spectre simulator. The proposed circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The working temperature of the proposed architecture is -60◦C to 85◦C. The temperature coefficients of the reference current generated from the proposed is 39.8 ppm/◦C at a supply voltage of 1.25V. The working supply voltage for proposed circuit ranges from 1.25 V to 2 V. The maximum power consumption of proposed circuit is 624.8nW at a supply voltage of 2V. The layout area of proposed reference circuit are 0.0013m2.

ABSTRACT. In this paper we report a development of the large signal model parameters extraction technique for gallium nitride (GaN) high electron mobility transistors (HEMT) from transient characteristics. An approach to nonlinear large-signal model parameter extraction of intrinsic model parameters namely capacitors CGS, CDS and CGD and extrinsic resistance RGS and RDS has been investigated. The extraction procedure is based on electronic circuit parametric simulation of the transient characteristics of the investigated equivalent circuit and evaluation of corresponding RC time constants. This technique is improved using appropriate polarity of the input pulses in dual-head Time Domain Reflectometry (TDR) system, configured also for Time Domain Transmission (TDT) measurements.

ABSTRACT. This paper presents an original technique to measure the noise figure of differential amplifiers with a four-port network analyzer. The approach is fast and simple as the S-parameters and the output noise powers are measured directly with the analyzer. There is no need of hybrid couplers or baluns. The measurement procedure and the test set-up are detailed in the paper. And to illustrate the usefulness of this new approach, measurement results of a radio-frequency differential amplifier are presented and compared to the results obtained with state-of-the-art techniques.

ABSTRACT. An accurate de-embedding method for millimeterwave and sub-millimeter-wave integrated circuits is presented. In this “Half-Thru” de-embedding method, the pad-interconnects parasitics effects are modeled as a Half-Thru structure from both parts of the device under test. Several de-embedding methods over millimeter and sub-millimeter wave frequencies are compared in integrated technology by considering S-CPW transmission lines as device under test. From these comparisons we propose an effective way to de-embed transmission lines. The S-CPW transmission line model and results are obtained from full-wave electromagnetic simulations in BiCMOS 55-nm technology.

ABSTRACT. A novel design combining embedded high dielectric constant dielectric resonator with planar technologies is presented in this paper. The utilization of dual-mode embedded resonators with high dielectric constant allows interesting miniaturization possibilities while maintaining a competitive filter performance. The proposed design is compatible with LTCC and, in general, any planar technology such as microstrip or coplanar waveguide.

ABSTRACT. Efficiency of mobile base stations became with the increasing number of users and services an important topic. Therefore efficiency enhancement methods such as the Doherty or Chireix combiner are experiencing a revival. Their performance heavily depends on the load modulation properties of the used RF transistors and unfortunately often falls behind the predicted theory, especially for high frequency operation. This paper analyses the impact of the different loss mechanisms of RF power transistors on their load modulation capabilities. Special attention was paid to the frequency dependent losses due to the limited Q-factor of the parasitic capacitance. Based on the example of a Doherty amplifier the importance of the load modulation properties for the efficiency in back off is highlighted.

ABSTRACT. We will present a comprehensive analysis of low frequency noise in InGaP /GaAs HBT transistor, which represents two main axes: first, we report a study of the low frequency noise characteristics of InGaP/GaAs HBT at different junction. Our measurements were performed over the frequency range from 100 Hz to 10 MHz, under different biasing conditions and over the temperature range from 300°K to 375°K. Low frequency generation recombination noise measurements revealed an electron trap with activation energy of 0.536eV. Then, from a rigorous physics-based noise simulation using the Langevin approach within the framework of Green’s function, traps detected by temperature-dependent experimental observation is located at the heterointerface -InGaP/GaAs, responsible for the GR noise sources

ABSTRACT. In this paper, we propose a novel programming technique, named R-SET pulse, in order to optimize the Low-Resistance State (LRS) performance of Ge-rich phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment of Ge2Sb2Te5. The R-SET pulse is capable of bringing the cell to its LRS at a lower switching threshold voltage than in the case of conventional programming pulses, thus protecting the cell from potential current overshoots during switching. The functionality of the circuit conceived to generate the R-SET pulse, which operates on a time reference scheme, is discussed. Simulations highlight the tunability of the produced R-SET pulse characteristics.

ABSTRACT. We present a design study for the fabrication of a fully depleted CMOS image sensor integrated on high-resistivity epitaxial layer. Both models and simulations are used and show that the maximal depleted thickness and the punch-trough current are dependent on the photo-diode cathode length. From these considerations, achievable performances are estimated

ABSTRACT. Transimpedance amplifiers (TIAs) are crucial elements in optical links. A simulation supported optimization study for different single ended TIAs was performed. Based on ST65nm CMOS technology, utilization scenario dependent solutions are presented, as well as an optimized solution for on-package multicore optical network receivers. A key result of our study is the superiority of the push-pull topology over the common source topology and we argue for optimizing TIAs for designated DC input currents.

ABSTRACT. Low frequency noise (LFN) in 0.13 µm BiCMOS SiGe:C was characterized both as a function of base current bias IB and emitter area Ae. The LFN exhibits typical behavior of 1/f noise for frequencies up to 1 KHz followed by the shot noise 2qI, in transistors with large emitter area (Ae>1 µm2). The 1/f noise is modeled following the SPICE compact model, and the LFN parameters KF and AF were calculated. The extracted figure of merit KB=KF*Ae has an excellent value of 1 10-10 µm2. The transistors with small emitter area (Ae<1 µm2) can be affected by the presence of generation-recombination (G-R) components. In some cases, where G-R presents large amplitude and high cut-off frequency, it is related to random telegraph signal (RTS).

ABSTRACT. A low-noise, custom-designed transimpedance amplifier has been developed to detect the current pulses (hundreds of pA) due to the features of a DNA molecule translocating via a nanopore, while handling DC currents (up to 100 nA). It is based on a CMOS current preamplifier designed to achieve high resolution with a wide bandwidth, thanks to the low parasitic capacitance of glass nanopipettes. With the aim of reducing the shot noise of the integrated amplifier, an auxiliary feedback network has been implemented. The electronic characterization confirms that fast current pulses modulating the DC current are detected. Validation experiments with DNA molecules demonstrate the actual resolution improvement with respect to the state-of-the-art.

ABSTRACT. This paper presents piezoresistive sensors array, developed by screen printing of polymer nanocomposites based on multiwall carbon nanotubes (MWCNT) in poly (dimethyl-siloxane) (PDMS) matrix. The sensors are printed on 25 µm thick flexible polyethylene terephthalate (PET) substrate in the form of segmental arrays with parallel plate structures, whereby, MWCNT/PDMS nanocomposites layer is sandwiched between two printed silver plates of 1×1 mm2 area each. Three different polymer nanocomposites (by wt. %) of carbon nanotubes (MWCNT) in PDMS matrix have been investigated here for possible application as a tactile sensor in an electronic skin for robots and general purpose applications.

ABSTRACT. ZnO nanoparticles thin films were deposited with different thicknesses on Kapton flexible substrates by drop coating method. The flexible platform consists in Ti/Pt interdigitated electrodes for gas detection and a heater device fabricated by Magnetron Sputtering and photolithography process. The thickness effects of the ZnO thin film on the gas sensing properties by ozone exposure at 200 °C has been studied. In order to test a deposit methodology used in large scale industrial production, an ultrasonic spray deposition was done. It was found that the sensitivity towards ozone gas is strongly dependent of the ZnO thin films thickness.

ABSTRACT. Phase Change Memory (PCM) is a non-volatile memory technology with wide programming window and continuously improving data retention performance. In order to drive the variable load PCM exhibits, the amplifier providing programming pulses to the cell must be able to accurately control pulse parameters. In this paper, we present a unity gain buffer capable of driving resistive loads varying up to three orders of magnitude. The buffer can replicate voltage pulses of amplitude up to 4.5 V with minimum rise and fall times. The study of the circuit behaviour in high-temperature environments demonstrates its accuracy over a temperature range from -50 °C up to 200 °C, enabling programming of PCM based on innovative materials in applications requiring reliable operation at high temperatures.

ABSTRACT. We report the design, simulations and measurements of two tunable analog equalizers. These circuits have been realized using indium phosphide heterojunction bipolar transistor reaching fT/fmax of 370/340 GHz. These analog equalizers provide a bandwidth of more than 100 GHz, depending on the settings. A varactor is used to tune the frequency response to equalize various types of 100-GBaud communication system channels.

ABSTRACT. The design methodology of low power current mode logic (CML) latches is described and the implementation of a D flip-flop (DFF) is presented in 28 nm CMOS technology. The DFF can work up to 22 Gbps full-rate with a bit error rate better than 10-12 and with a power consumption of only 880 µW. Since the circuit is inductor-less the area of the circuit is only 25 µm × 10 µm. As a further implementation of the CML latches a very low power static frequency divider with quadrature outputs in 28 nm is presented. It divides the clock signal up to 26 GHz and has only 880 µW power consumption. To our knowledge, with 0.034 mW/GHz, this static frequency divider has one of the best figure of merit reported to date.

ABSTRACT. This paper proposes the design of an integrated fast settling analog frontend for application in wireless wake-up receivers. The chip includes a low noise amplifier with transformer and integrated balun, a multi-hyperbolic tangent gilbert cell mixer with Sallen-Key filter, a limiting amplifier and a LC-cross coupled digital-controlled oscillator. The chain exhibits a measured conversion gain of 29dB with a current of only 3.3mA in its on-mode. The measured input return loss is -19dB at 2.4GHz with a corresponding double sideband noise figure of 7.6dB at an intermediate frequency of 51MHz. All circuits enable on/off switching which allows operation within on-times of 200ns. The chain is optimized to settle in less than 60ns until the output obtains -1dB of its steady state amplitude.

ABSTRACT. A low-noise CMOS Image Sensor based on a 10-bit two-step Single Slope A/D Converter (SS-ADC) with Hybrid CDS is proposed. In order to reduce the pixel noise, a Hybrid CDS is discussed. With this technique, Column Fixed Pattern Noise(CFPN) is drastically reduced by about 55% or more, compared to that of analog CDS only. Furthermore, to overcome low conversion speed of SS-ADC , two-step SS-ADC is proposed. The proposed CIS has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA resolution. The fabricated chip size is 5mm x 3mm, and the power consumption is about 35mW at 3.3V supply voltage. The measured CFPN is 0.8LSB, and the frame rate is 220 frames/s.