NANOARCH2018: INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES 2018

This page contains an index consisting of author-provided keywords.

2
2.5-D Integration	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
4
4T bitcell	Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28 nm 3D CoolCubeTM Technology
A
adaptive systems	Real-Time Trainable Data Converters for General Purpose Applications
Adder	Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices
aging	An aging resilient neural network arcitecture
Analog-to-digital conversion	Real-Time Trainable Data Converters for General Purpose Applications
approximate multiplier	A Probabilistic Error Model and Framework for Approximate Booth Multipliers
Approximate Store	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
B
BDD	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Bias Scheme	Minimal Disturbed Bits in Writing Resistive Crossbar Memories
binary decision diagrams	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Bipolar ReRAM	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
BlackOut	Fast Estimations of Failure Probability Over Long Time Spans
BNN	Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning
boolean functions	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Boolean logic operations	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
Boolean methods	Size Optimization of MIGs with an Application to QCA and STMG Technologies
Booth encoding	A Probabilistic Error Model and Framework for Approximate Booth Multipliers
botton-up designless networks	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
BTI	Fast Estimations of Failure Probability Over Long Time Spans
C
CAD	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Carbon-Nanoelectronics	Complementary Arranged Graphene Nanoribbon-based Boolean Gates
circuit synthesis	Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution
Combinational circuits	Size Optimization of MIGs with an Application to QCA and STMG Technologies
Computer Aided Design	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
computing in-memory	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Conductance Map	Complementary Arranged Graphene Nanoribbon-based Boolean Gates
Content Addressable Memory	Ring-Shaped Racetrack Memory: From Circuits and Systems Perspective
Cross-point	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation
cross-point array	Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
Cross-talk Computing	A Novel Analog to Digital Conversion Concept with Crosstalk Computing
crossbar	Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Crossbar architecture	Quantum-dot Cellular Automata RAM design using Crossbar Architecture
Crossbar array	Minimal Disturbed Bits in Writing Resistive Crossbar Memories
Crossbar Arrays	Integrated Synthesis Methodology for Crossbar Arrays
Crosstalk Computing	Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
current calibration	An aging resilient neural network arcitecture
D
d-latch	Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
Defect Tolerance	Integrated Synthesis Methodology for Crossbar Arrays
digital system taxonomy	A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
digital-to-analog conversion	Real-Time Trainable Data Converters for General Purpose Applications
DWM	Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
E
endurance	CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
Energy Efficiency	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
Energy modeling and analysis	Power Analysis of an mRNA-Ribosome System
errors	CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
F
Fault Tolerance	Integrated Synthesis Methodology for Crossbar Arrays
FBDD	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
finite automata	Regular Expression Matching with Memristor TCAMs for Network Security
Firing Squad Synchronization problem	Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits
functional programming	A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
G
GNR	Complementary Arranged Graphene Nanoribbon-based Boolean Gates
Graphene	Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices Complementary Arranged Graphene Nanoribbon-based Boolean Gates
Graphene Quantum Point Contact	Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices
Graphene-based Boolean Gates	Complementary Arranged Graphene Nanoribbon-based Boolean Gates
H
Hardware acceleration	Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
I
in-memory computation	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation
in-Memory computing	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Interconnect	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
Interposer	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
L
L2 Cache	Ring-Shaped Racetrack Memory: From Circuits and Systems Perspective
Large Scale Circuits	Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits
logic design	Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
logic gates	Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
Logic synthesis	Integrated Synthesis Methodology for Crossbar Arrays Size Optimization of MIGs with an Application to QCA and STMG Technologies
Low Swing	Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
Low-Power Circuits	A Novel Analog to Digital Conversion Concept with Crosstalk Computing
M
machine learning	Real-Time Trainable Data Converters for General Purpose Applications
Majority-inverter graphs	Size Optimization of MIGs with an Application to QCA and STMG Technologies
Memory	Quantum-dot Cellular Automata RAM design using Crossbar Architecture
memristor	An aging resilient neural network arcitecture Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning Regular Expression Matching with Memristor TCAMs for Network Security Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Memristor Arrays	Integrated Synthesis Methodology for Crossbar Arrays
memristors	Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator Real-Time Trainable Data Converters for General Purpose Applications
MFCC	Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition
Mixed signal domain hardware optimization	Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition
Molecular-Nanoparticle hybrids	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
MRAM	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation
mRNA-Ribosome System	Power Analysis of an mRNA-Ribosome System
multi-junction networks	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
Multi-Valued Logic	Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices
multilevel cell memories	CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
N
Nanoelectornics	Quantum-dot Cellular Automata RAM design using Crossbar Architecture
nanoelectrodes	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
Nanoelectronics	Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits
network security	Regular Expression Matching with Memristor TCAMs for Network Security
Neural network	An aging resilient neural network arcitecture
neuromorphic computing	Real-Time Trainable Data Converters for General Purpose Applications
Next generation non volatile memories	CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
Non-Volatile Flip-Flop (NVFF)	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
nonlinear single electron transistors percolation	Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
P
parallel architecture	A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
Parallel computing	A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
Performance Optimization	Integrated Synthesis Methodology for Crossbar Arrays
Polymorphic Crosstalk Logic circuits	Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
Probabilistic error model	A Probabilistic Error Model and Framework for Approximate Booth Multipliers
processing in-memory	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Q
quantum computing	Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution
Quantum simulators	Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator
Quantum-dot Cellular Automata (QCA)	Quantum-dot Cellular Automata RAM design using Crossbar Architecture Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits
Qubits	Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator
R
Racetrack memory	Ring-Shaped Racetrack Memory: From Circuits and Systems Perspective
RAM	Quantum-dot Cellular Automata RAM design using Crossbar Architecture
reconfigurable architectures	Real-Time Trainable Data Converters for General Purpose Applications
Reconfigurable Crosstalk Logic	Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
recursive functions	A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
regular expression matching	Regular Expression Matching with Memristor TCAMs for Network Security
ReRAM Degradation	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
ReRAM Endurance	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
Resistive memories	Minimal Disturbed Bits in Writing Resistive Crossbar Memories
resource estimation	Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution
Ribosomal Computing	Power Analysis of an mRNA-Ribosome System
Ring shaped	Ring-Shaped Racetrack Memory: From Circuits and Systems Perspective
RRAM	Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning
Run-Time Tunable Resistive States	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
S
sequential circuits	Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
Sequential Logic	Power Analysis of an mRNA-Ribosome System
Size optimization	Size Optimization of MIGs with an Application to QCA and STMG Technologies
Sneak path	Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning
sparse coding	Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
Speech recognition	Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition
spin-diodes	Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
spintronic device	Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
spintronics	Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
sr-latch	Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
SRAM	Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28 nm 3D CoolCubeTM Technology
surface code	Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution
synapse	An aging resilient neural network arcitecture
synaptic current	An aging resilient neural network arcitecture
Synchronization	Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits
synthesis of crossbars	Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
T
TCAM	Regular Expression Matching with Memristor TCAMs for Network Security
Tree network	A Novel Analog to Digital Conversion Concept with Crosstalk Computing
U
ULV	Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28 nm 3D CoolCubeTM Technology
V
Variability	Fast Estimations of Failure Probability Over Long Time Spans
variability-aware design	Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
Variation	Fast Estimations of Failure Probability Over Long Time Spans
VCMA	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation
W
Wire resistance	Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning
Write disturb	Minimal Disturbed Bits in Writing Resistive Crossbar Memories
Write-Termination	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
Writing	Minimal Disturbed Bits in Writing Resistive Crossbar Memories

Disclaimer | Powered by EasyChair Smart Program