FPL 2021: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS

This page contains an index consisting of author-provided keywords.

1
100 Gbps TCP/IP	EasyNet: 100 Gbps Network for HLS
2
2-level mux	Two-level MUX Design and Exploration in FPGA Routing Architecture
4
4K
A
Acceleration	OpenCL-based FPGA accelerator for semi-global approximate string matching DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays *An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
accelerator	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration *An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Active Headrest	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
aggregation	A Specialized Memory Hierarchy for Stream Aggregation
Aging	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
AI	Dense FPGA Compute using Signed Byte Tuples
Alignment	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
ANC	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
application mapping	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays
Approximate Computing	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Approximate counting	Speed Records in Network Flow Measurement on FPGA
arbiter PUF	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
architecture	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
arithmetic	Dense FPGA Compute using Signed Byte Tuples
Artificial Neural Networks	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
ASIC	Accelerating Continual Learning on Edge FPGA Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
ASIR	Wormhole Computing in Networks-on-Chip
asP* handshake protocol	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
B
benchmark	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
big data	A RISC-V softcore optimised for exploring custom SIMD instructions
Bilateral Filter	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
Bilateral Grid	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
Bioinformatics	OpenCL-based FPGA accelerator for semi-global approximate string matching
Bit-serial	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Bitstream generator
C
cache hierarchy	A RISC-V softcore optimised for exploring custom SIMD instructions
cad	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
CAPI	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
carry chain	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
CGRA	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays
Channel Decoding	Optimizing Deep Learning Decoders for FPGA Implementation
Circuit Design	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Classic McEliece	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
clock gating	Power-Aware Computing Systems on FPGAs: A Survey
Clock skew scheduling	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
clock-domain crossing (CDC)	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
CNN	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
CNN accelerator	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
co-design	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Coarse-Grained Reconfigurable Array
Code Generation	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
Compiler	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Computational Complexity	Optimizing Deep Learning Decoders for FPGA Implementation
Compute Tomography	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
computer architecture	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Computer Arithmetic	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Computer vision	Accelerating Continual Learning on Edge FPGA
connected component labelling (CCL)
Continual learning	Accelerating Continual Learning on Edge FPGA
Convolution	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration
Convolution neural networks	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
convolutional neural network	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures *End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution *An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Convolutional Neural Networks	Towards the Efficient Multi-Platform Execution of Deep Neural Networks Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
CPS	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
cross-correlation	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification
Cryptographic Key	CHOICE – A Tunable PUF-Design for FPGAs
Cryptography	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
custom instructions	A RISC-V softcore optimised for exploring custom SIMD instructions
custom SIMD instructions
D
data converter	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
dataflow	A Specialized Memory Hierarchy for Stream Aggregation
Deep Learning	Accelerating Continual Learning on Edge FPGA MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research Optimizing Deep Learning Decoders for FPGA Implementation
Deep Neural Network	Distributed Recommendation Inference on FPGA Clusters
Deep neural networks	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
Deep Reinforcement Learning
Denoising Filter	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
Design Automation	Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs
Design Methodology	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Design Space Exploration	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Digital hardware design
Digital Signal Processing	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Distributed FPGA Applications	EasyNet: 100 Gbps Network for HLS
Distributed FPGAs
Distributed Systems	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
DNN compression	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
DPU	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
DSP Systems	Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
DVFS	Power-Aware Computing Systems on FPGAs: A Survey
dynamic undervolting
Dynamic voltage and frequency scaling	Offloading Methodologies for Power-Aware Real-time Operating Systems
E
E-learning
education	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
eFPGA
ElGamal Cryptosystem	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Elliptic Curve Cryptography	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Embedded	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
Embedded Hardware	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
embedded systems	An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
Emerging memory technologies	FPGA-based Hyrbid Memory Emulation System
Energy estimation	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
Error	An Emulation of Quantum Error-Correction on an FPGA device
F
Fast Constant-Time GCD Algorithm	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
fault diagnosis	Power-Aware Computing Systems on FPGAs: A Survey
Feedback FxLMS	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
FER	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Field Programmable Gate Arrays	OpenCL-based FPGA accelerator for semi-global approximate string matching
field programmable gate arrays (FPGA)	Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures
Field Programmable Gate Arrays (FPGAs)	Pharos: a Multi-FPGA Performance Monitor
field-programmable	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
field-programmable gate array	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
Fixed-point	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Fixed-point Simulation	Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
Flash controller	A High-performance Open-channel Open-way NAND Flash Controller Architecture
formal verification	(Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
FPGA	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications A RISC-V softcore optimised for exploring custom SIMD instructions RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access Two-level MUX Design and Exploration in FPGA Routing Architecture CHOICE – A Tunable PUF-Design for FPGAs EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration Speed Records in Network Flow Measurement on FPGA OpenCL-based FPGA accelerator for semi-global approximate string matching An Emulation of Quantum Error-Correction on an FPGA device DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution Performance assessment of FPGAs as HPC accelerators using the FER benchmark Accelerating Continual Learning on Edge FPGA *An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics Distributed Recommendation Inference on FPGA Clusters A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms A High-performance Open-channel Open-way NAND Flash Controller Architecture Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework HALF: Holistic Auto Machine Learning for FPGAs Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research Towards the Efficient Multi-Platform Execution of Deep Neural Networks Wormhole Computing in Networks-on-Chip Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
FPGA Acceleration	Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
FPGA accelerator	FPGA-based Hyrbid Memory Emulation System
FPGA Architecture	*Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
FPGA Implementation	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications Optimizing Deep Learning Decoders for FPGA Implementation
FPGA mapping	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
FPGA Middleware
FPGA Network	EasyNet: 100 Gbps Network for HLS
FPGA overlay	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
FPGA SoC	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
FPGA tools	Pharos: a Multi-FPGA Performance Monitor
FPGA Virtualization	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
FPGAs	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
G
GCD	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
genomics	OpenCL-based FPGA accelerator for semi-global approximate string matching *An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
globally asynchronous locally synchronous (GALS)	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
GPU	DO-GPU: A Domain Optimizable General-Purpose Soft GPU Towards the Efficient Multi-Platform Execution of Deep Neural Networks
graph sampling	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
GRU	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
H
Hardware	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Hardware Acceleration	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Hardware accelerator	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Hardware Design	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Hardware emulation	FPGA-based Hyrbid Memory Emulation System
Hardware Library	HALF: Holistic Auto Machine Learning for FPGAs
Hardware Multiplier	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
hardware security	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Hardware/Software co-design	CHOICE – A Tunable PUF-Design for FPGAs HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
HBM	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
HDL
Heterogeneous Computing
Heterogeneous platform	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Heuristic	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
High level synthesis	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
high-level synthesis	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs (Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
High-Level-Synthesis	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
High-Speed implementation	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
HLS	Performance assessment of FPGAs as HPC accelerators using the FER benchmark EasyNet: 100 Gbps Network for HLS Towards the Efficient Multi-Platform Execution of Deep Neural Networks
Homomorphic Encryption	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
HW/SW Co-Design	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
Hypervisor	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
I
I/O Scheduling	A High-performance Open-channel Open-way NAND Flash Controller Architecture
Image Classification	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
Image Processing	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
Incremental learning	Accelerating Continual Learning on Edge FPGA
Integrate and Fire	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Inter-variable dependency	An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
Internet of Things	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
IoT	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
IoT-23 Dataset	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
L
LFSR	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
LiDAR
Lifelong deep learning	Accelerating Continual Learning on Edge FPGA
Light-weight implementation	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Logging Framework
loop pipelining	(Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
Low-Power	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
LSTM	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications *Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
M
Machine Learning	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Machine Learning Inference	Distributed Recommendation Inference on FPGA Clusters MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
majority-inverter gate representation	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
many-core architecture	Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures
memory access analysis	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
memory system	FPGA-based Hyrbid Memory Emulation System
memory-hierarchy	A Specialized Memory Hierarchy for Stream Aggregation
micro-architecture	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification
mixed precision	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
Mixed-Integer Linear Programming	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
MLP	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
MobileNet	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Model-Based	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
Model-checking	Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA
modeling attack	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Modular Inverse	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
MPI	EasyNet: 100 Gbps Network for HLS
MPSoC	Wormhole Computing in Networks-on-Chip
Multi-FPGA Systems	Pharos: a Multi-FPGA Performance Monitor
Multiple Channels	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
multipliers	Dense FPGA Compute using Signed Byte Tuples
N
NAND Flash	A High-performance Open-channel Open-way NAND Flash Controller Architecture
NAS	HALF: Holistic Auto Machine Learning for FPGAs
Negotiation-Based Routing	*Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Network flow measurement	Speed Records in Network Flow Measurement on FPGA
Network-attached Accelerator
networks-on-chip (NoC)	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
Neural Architecture Search	HALF: Holistic Auto Machine Learning for FPGAs
Neural Network	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Neural Networks	Optimizing Deep Learning Decoders for FPGA Implementation
Neuromorphic Computing	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
NoC	Wormhole Computing in Networks-on-Chip
non-maximum suppression	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
NVM	FPGA-based Hyrbid Memory Emulation System
O
Object detection	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
OmpSs@FPGA	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Online learning	Accelerating Continual Learning on Edge FPGA
Open-source
open-source hardware
OpenCL	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
optical time-domain reflectometry	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
Overlay	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
P
Parallel Architectures	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Parallelism	A High-performance Open-channel Open-way NAND Flash Controller Architecture
Partial Reconfiguration	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration
performance	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Performance Monitoring	Pharos: a Multi-FPGA Performance Monitor
Physical design
PointPillars
Post-Quantum Cryptography	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Power Efficiency	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
power estimator	Power-Aware Computing Systems on FPGAs: A Survey
power gating	Power-Aware Computing Systems on FPGAs: A Survey
Power-aware system architecture	Offloading Methodologies for Power-Aware Real-time Operating Systems
prefix scan	A RISC-V softcore optimised for exploring custom SIMD instructions
Printing in FPGA
Privacy Preserving Computation	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
probabilistic data structure	Speed Records in Network Flow Measurement on FPGA
Processor array	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
protein identification	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification
PUF	CHOICE – A Tunable PUF-Design for FPGAs
PYNQ
Q
QAM Demodulation	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Quantization	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Quantum	An Emulation of Quantum Error-Correction on an FPGA device
R
radio
random walk	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Real-Time	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
Real-time operating system	Offloading Methodologies for Power-Aware Real-time Operating Systems
real-time video processing
Recommendation System	Distributed Recommendation Inference on FPGA Clusters
reconfigurable	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
reconfigurable computing	Pharos: a Multi-FPGA Performance Monitor Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures
Reconfigurable Hardware Design	Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
reconfiguration	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays
Reliability	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Resource constrained devices	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
RFSoC
RISC-V	A RISC-V softcore optimised for exploring custom SIMD instructions RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Robotics	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
Roofline	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Routing	Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs
routing architecture	Two-level MUX Design and Exploration in FPGA Routing Architecture
RSA	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Runtime	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
RVfpga	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
RVfpga-SoC	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
S
SAT solver	An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
Security	CHOICE – A Tunable PUF-Design for FPGAs FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
Shor	An Emulation of Quantum Error-Correction on an FPGA device
Siamese neural network
SIMD	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications A RISC-V softcore optimised for exploring custom SIMD instructions
Sketch	Speed Records in Network Flow Measurement on FPGA
SoC	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Soft Core	Towards the Efficient Multi-Platform Execution of Deep Neural Networks
soft GPU	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
softcore	A RISC-V softcore optimised for exploring custom SIMD instructions
sorting	A RISC-V softcore optimised for exploring custom SIMD instructions
sparsity	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
specialization	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
spectrum analysis
Spiking Neural Networks	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
stream-processing	A Specialized Memory Hierarchy for Stream Aggregation
streaming	A RISC-V softcore optimised for exploring custom SIMD instructions
Streaming learning	Accelerating Continual Learning on Edge FPGA
Swarm Verification	Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA
SweRV	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
SweRVolf	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Switch Blocks	*Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
synchronization	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
synchronizing FIFO	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
Synopsys	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
System-On-Chip	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education Towards the Efficient Multi-Platform Execution of Deep Neural Networks
systolic array	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
T
template
time-variant obfuscation	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Timing Analysis	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
TOPs	Dense FPGA Compute using Signed Byte Tuples
tracking
U
UHD
undervolting
V
VHDL	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Virtual Machine	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
Vitis	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
W
weight pruning	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
WFA	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
X
Xilinx	An Emulation of Quantum Error-Correction on an FPGA device Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Z
Zynq UltraScale+ MPSoC

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