Days: Wednesday, September 1st Thursday, September 2nd Friday, September 3rd
View this program: with abstractssession overviewtalk overview
| 16:30 | *Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge (abstract) |
| 16:50 | FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access (abstract) |
| 17:10 | *An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics (abstract) |
| 17:30 | A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications (abstract) |
| 17:40 | DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays (abstract) |
| 17:50 | MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks (abstract) |
| 16:30 | CHOICE – A Tunable PUF-Design for FPGAs (abstract) |
| 16:50 | Power-Aware Computing Systems on FPGAs: A Survey (abstract) |
| 17:10 | HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem (abstract) |
| 17:30 | Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme (abstract) |
| 17:40 | EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs (abstract) |
| 17:50 | FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT (abstract) |
| 19:00 | *End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression (abstract) |
| 19:20 | Performance assessment of FPGAs as HPC accelerators using the FER benchmark (abstract) PRESENTER: Enrico Calore |
| 19:40 | A High-performance Open-channel Open-way NAND Flash Controller Architecture (abstract) |
| 20:00 | Communication-optimized micro-architecture to compute Xcorr scores for peptide identification (abstract) |
| 20:10 | An Emulation of Quantum Error-Correction on an FPGA device (abstract) |
| 20:20 | OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration (abstract) |
| 19:00 | Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution (abstract) |
| 19:20 | Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications (abstract) |
| 19:40 | Dense FPGA Compute using Signed Byte Tuples (abstract) |
| 20:00 | A RISC-V softcore optimised for exploring custom SIMD instructions (abstract) |
| 20:10 | DO-GPU: A Domain Optimizable General-Purpose Soft GPU (abstract) |
| 20:20 | RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education (abstract) |
View this program: with abstractssession overviewtalk overview
| 16:30 | *An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment (abstract) |
| 16:50 | Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset (abstract) |
| 17:10 | An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising (abstract) |
| 17:30 | OpenCL-based FPGA accelerator for semi-global approximate string matching (abstract) |
| 17:40 | An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies (abstract) |
| 17:50 | Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA (abstract) |
| 16:30 | FPGA-based Hyrbid Memory Emulation System (abstract) |
| 16:50 | EasyNet: 100 Gbps Network for HLS (abstract) |
| 17:10 | A Specialized Memory Hierarchy for Stream Aggregation (abstract) |
| 17:30 | Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators (abstract) |
| 17:50 | Speed Records in Network Flow Measurement on FPGA (abstract) |
| 19:00 | *Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence (abstract) |
| 19:20 | Two-level MUX Design and Exploration in FPGA Routing Architecture (abstract) PRESENTER: Yuhang Shen |
| 19:40 | Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs (abstract) |
| 20:00 | A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems (abstract) |
| 20:20 | Pharos: a Multi-FPGA Performance Monitor (abstract) |
| 19:00 | Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators (abstract) |
| 19:10 | Offloading Methodologies for Power-Aware Real-time Operating Systems (abstract) |
| 19:20 | Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures (abstract) |
| 19:30 | A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays (abstract) |
| 19:40 | Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications (abstract) |
| 19:50 | Optimizing Deep Learning Decoders for FPGA Implementation (abstract) |
| 20:00 | Wormhole Computing in Networks-on-Chip (abstract) |
| 20:10 | Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures (abstract) |
| 20:20 | Towards the Efficient Multi-Platform Execution of Deep Neural Networks (abstract) |
View this program: with abstractssession overviewtalk overview
| 16:30 | Distributed Recommendation Inference on FPGA Clusters (abstract) |
| 16:50 | SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs (abstract) |
| 17:10 | Accelerating Continual Learning on Edge FPGA (abstract) |
| 17:30 | Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures (abstract) |
| 17:40 | Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration (abstract) |
| 16:30 | Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs (abstract) |
| 16:50 | A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms (abstract) |
| 17:10 | Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming (abstract) |
| 17:30 | Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation (abstract) |
| 17:50 | (Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining (abstract) |
| 19:00 | MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications (abstract) |
| 19:20 | Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research (abstract) |
| 19:40 | HALF: Holistic Auto Machine Learning for FPGAs (abstract) |
| 19:50 | MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework (abstract) |
1. Marcelo Brandalero, Mitko Veleski, Hector Gerardo Munoz Hernandez, Muhammad Ali, Laurens Le Jeune, Toon Goedem´e, Nele Mentens, Jurgen Vandendriessche, Lancelot Lhoest, Bruno da Silva, Abdellah Touhafi, Diana Gohringer, Michael Hubner. AITIA: Embedded AI Techniques for Embedded Industrial Applications
2. Suranga Handagala, Martin Herbordt, Miriam Leeser. OCT: The Open Cloud FPGA Testbed
3. Konstantina Koliogeorgi, Fekhr Eddine Keddous, Dimosthenis Masouros, Antony Chazapis, Sotirios Xydis, Angelos Bilas, Jean-Thomas Acquaviva, Huy Nam Nguyen, Dimitrios Soudris. FPGA acceleration in EVOLVE’s Converged Cloud-HPC Infrastructure
4. Nikolaos Bellas, Christos D. Antonopoulos, Spyros Lalis, Maria-Rafaela Gkeka, Alexandros Patras, Georgios Keramidas, Iakovos Stamoulis, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos Trahanias, Paul Zikas, George Papagiannakis, Ioanna Kartsonaki. Architectures for SLAM and Augmented Reality Computing
5. Philipp Kasgen, Mohamed Messelka and Markus Weinhardt. HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler
6. Jürgen Becker, Leonard Masing, Tobias Dörr, Florian Schade, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios Kelefouras, Konstantinos Antonopoulos, Nikolaos Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Florian Oszwald, Dominik Reinhardt, Mohamad Chamas, Adnan Bekan, Graham Smethurst, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales. XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems
7. Angelos S. Voros, Christos Panagiotou, Stavros Zogas, Georgios Keramidas, Christos P. Antonopoulos, Michael Hubner, Nikolaos S. Voros. The SMART4ALL High Performance Computing Infrastructure: Sharing high end hardware resources via cloud-based microservices