FPL 2021: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS

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Aaraj, Najwa	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Aguado, Quim	OpenCL-based FPGA accelerator for semi-global approximate string matching
Ai, Baole	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Akgün, Gökhan	Power-Aware Computing Systems on FPGAs: A Survey Offloading Methodologies for Power-Aware Real-time Operating Systems
Alachiotis, Nikolaos	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration
Ali, Muhammad	Power-Aware Computing Systems on FPGAs: A Survey
Alonso, Gustavo	Distributed Recommendation Inference on FPGA Clusters EasyNet: 100 Gbps Network for HLS
Alvarez, Lluc	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment OpenCL-based FPGA accelerator for semi-global approximate string matching
Anderson, Jason	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
Andrews, David	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Arora, Aman	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Aung Myat, Thu Linn	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
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Balakrishnan, M.	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
Basalama, Suhail	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Becher, Andreas	CHOICE – A Tunable PUF-Design for FPGAs
Betz, Vaughn	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Borda, Aatman	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Boutros, Andrew	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Brandalero, Marcelo	Towards the Efficient Multi-Platform Execution of Deep Neural Networks
Brown, Stephen Dean	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
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Calore, Enrico	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Cao, Yu	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Castells-Rufas, David	OpenCL-based FPGA accelerator for semi-global approximate string matching
Chang, Zhengtai	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Chaver, Daniel	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Chen, Jeffrey	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Cheng, Bowen	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Cheng, Jianyi	(Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
Cheung, Ray C.C.	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Chiou, Derek	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Chow, Paul	Pharos: a Multi-FPGA Performance Monitor
Constantinides, George	(Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
D
Damghani, Seyed	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Dasu, Aravind	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Deshpande, Sanjay	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Diakite, Daouda	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
Diamantopoulos, Dionysios	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
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Ebrahimi, Milad	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Espinosa-Morales, Antonio	OpenCL-based FPGA accelerator for semi-global approximate string matching
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Fan, Wenbing	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Fang, Zhenman	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Farràs, Oriol	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Finn, Simon	Dense FPGA Compute using Signed Byte Tuples
Fournier, Emilien	Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA
Fricke, Florian	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays
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Gac, Nicolas	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
Ganusov, Ilya	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
Ghavami, Behnam	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Gillan, Charles	An Emulation of Quantum Error-Correction on an FPGA device
Goel, Shikha	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
Goh, Rick Siow Mong	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Gomez-Perez, J. I.	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Gratz, Paul	FPGA-based Hyrbid Memory Emulation System
Gribok, Sergey	Dense FPGA Compute using Signed Byte Tuples
Göhringer, Diana	Power-Aware Computing Systems on FPGAs: A Survey Offloading Methodologies for Power-Aware Real-time Operating Systems Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems Wormhole Computing in Networks-on-Chip
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Haghi, Abbas	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Hagleitner, Christoph	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Hall, Mathew	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Hansen, Patrick	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Hara-Azumi, Yuko	An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
Harris, Sarah L.	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Hart, Michael	An Emulation of Quantum Error-Correction on an FPGA device
Hashimoto, Nobuho	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
He, Lei	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
He, Warrick	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
He, Zhenhao	EasyNet: 100 Gbps Network for HLS
He, Zhenhao	Distributed Recommendation Inference on FPGA Clusters
Hernandez Luz, Carles	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Hong, Sehwan	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Hsiao, Hsu-Chun	Speed Records in Network Flow Measurement on FPGA
Hsu, Jia-Ching	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Hübner, Michael	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures Towards the Efficient Multi-Platform Execution of Deep Neural Networks
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Ibrahim, Mohamed	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Ienne, Paolo	*Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Irmak, Hasan	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration
Ishimwe, Ange-Thierry	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
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Jiang, Wenqi	Distributed Recommendation Inference on FPGA Clusters
John, Lizy	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Jun, Sang-Woo	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
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Kakakhel, Zubair	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Kamaleldin, Ahmed	Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures
Kannan, Rajgopal	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
Kate, Sangram	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Kavvousanos, Emmanouil	Optimizing Deep Learning Decoders for FPGA Implementation
Kelly, Paul H J	A RISC-V softcore optimised for exploring custom SIMD instructions
Kent, Kenneth	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Kim, Jin Hee	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
Kindgren, Olof	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Klauer, Bernd	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Klemd, Alexander	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Korolija, Dario	EasyNet: 100 Gbps Network for HLS
Kostalampros, Vatistas	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Krueger, Jens	HALF: Holistic Auto Machine Learning for FPGAs
Krüger, Paul	CHOICE – A Tunable PUF-Design for FPGAs
Kumar, Aayan	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Kumar, Sumesh	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification
Kuppannagari, Sanmukh R.	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
Kuzhively, Ajay	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
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Lagadec, Loic	Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA
Lam, Siew Kei	Accelerating Continual Learning on Edge FPGA
Langhammer, Martin	Dense FPGA Compute using Signed Byte Tuples DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Leon, Vasileios	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Li, He	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
Li, Jian	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
Liang, Hao	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Liaqat, M. Hamza	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Liu, Lin Qiao	Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
Liu, Qiang	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Liu, Zhengyan	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Loroch, Dominik	HALF: Holistic Auto Machine Learning for FPGAs
Lu, Yu Shen	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
Luk, Wayne	A RISC-V softcore optimised for exploring custom SIMD instructions
Luo, Tao	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
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M.S. Abdelhadi, Ameer	Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
Ma, Rui	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Mandebi Mbongue, Joel	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Manzano, Marc	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Marco-Sola, Santiago	OpenCL-based FPGA accelerator for semi-global approximate string matching
Marco-Sola, Santiago	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Martelli, Maxime	OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
Mateu, Victor	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Mauldin, Thomas	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
McAllister, John	An Emulation of Quantum Error-Correction on an FPGA device
Mehta, Samidh	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Meng, Jian	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Mentens, Nele	Speed Records in Network Flow Measurement on FPGA
Merino del Pozo, Santos	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Mohanty, Abinash	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Moon, Jinyeong	*Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Moreto, Miquel	*An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem OpenCL-based FPGA accelerator for semi-global approximate string matching
Moure, Juan Carlos	OpenCL-based FPGA accelerator for semi-global approximate string matching
Murphy, Colin	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
Muñoz Hernandez, Hector Gerardo	Towards the Efficient Multi-Platform Execution of Deep Neural Networks
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Na, Anupreetham	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Ney, Jonas	HALF: Holistic Auto Machine Learning for FPGAs
Ngo, Duc-Minh	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
Nguyen, Anh Hoang Ngoc	An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
Nikolic, Stefan	*Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Nurvitadhi, Eriko	*End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression DO-GPU: A Domain Optimizable General-Purpose Soft GPU
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Owen, Robert	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
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Paliouras, Vassilis	Optimizing Deep Learning Decoders for FPGA Implementation
Panahi, Atiyehsadat	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
Panchapakesan, Sathish	SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
Papaphilippou, Philippos	A RISC-V softcore optimised for exploring custom SIMD instructions
Pasca, Bogdan	Dense FPGA Compute using Signed Byte Tuples
Patel, Pragnesh	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Pekmestzi, Kiamal	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Perrig, Adrian	Speed Records in Network Flow Measurement on FPGA
Piyasena, Duvindu	Accelerating Continual Learning on Edge FPGA
Piñuel, Luis	RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Podlubne, Ariel	Reconfigurable Computing Systems as Component-oriented Designs for Robotic Applications
Popovici, Emanuel	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
Prasanna, Viktor K.	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
Pratap Ghanathe, Nikhil	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
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Qian, Jiadong	Two-level MUX Design and Exploration in FPGA Routing Architecture
Qin, Mian	FPGA-based Hyrbid Memory Emulation System
Qiu, Yunhui	A High-performance Open-channel Open-way NAND Flash Controller Architecture
Qu, Chuping	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
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Rafii, Arzhang	Pharos: a Multi-FPGA Performance Monitor
Rajen, Aishwarya	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Ramakrishnan Geethakumari, Prajith	A Specialized Memory Hierarchy for Stream Aggregation
Rauch, Daniel	Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Reddy, Narasimha	FPGA-based Hyrbid Memory Emulation System
Rettkowski, Jens	Wormhole Computing in Networks-on-Chip
Ribes-González, Jordi	HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Rogers, Leo	An Emulation of Quantum Error-Correction on an FPGA device
Rybalkin, Vladimir	HALF: Holistic Auto Machine Learning for FPGAs
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Sachau, Delf	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Saeed, Fahad	Communication-optimized micro-architecture to compute Xcorr scores for peptide identification
Sateesan, Arish	Speed Records in Network Flow Measurement on FPGA
Scherrer, Simon	Speed Records in Network Flow Measurement on FPGA
Schifano, Sebastiano Fabio	Performance assessment of FPGAs as HPC accelerators using the FER benchmark
Schlumberger, Jens	CHOICE – A Tunable PUF-Design for FPGAs
Sen, Rijurekha	EnergyNN: Energy estimation for Neural Network Inference tasks on DPUs
Seo, Jae-sun	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access *End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Seshadri, Vivek	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Shahin, Keyvan	A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
Shannon, Lesley	MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Sharma, Rahul	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Shen, Minghua	Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs
Shen, Wenting	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Shen, Yuhang	Two-level MUX Design and Exploration in FPGA Routing Architecture
Shi, Kaichuang	Two-level MUX Design and Exploration in FPGA Routing Architecture
Shi, Shanshan	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Song, Binwei	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Soudris, Dimitrios	Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Sourdis, Ioannis	A Specialized Memory Hierarchy for Stream Aggregation
Streit, Franz-Josef	CHOICE – A Tunable PUF-Design for FPGAs
Su, Chunyou	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Sun, Welson	Pharos: a Multi-FPGA Performance Monitor
Szefer, Jakub	Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
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Takamaeda-Yamazaki, Shinya	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
Tan, Tian	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Teich, Jürgen	CHOICE – A Tunable PUF-Design for FPGAs
Temko, Andriy	FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
Teodorov, Ciprian	Carnac: Algorithm Variability for Fast Swarm Model-Checking on FPGA
Timmermann, Johannes	A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
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Venkataramanaiah, Shreyas Kolala	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Vivekanandham, Rajesh	DO-GPU: A Domain Optimizable General-Purpose Soft GPU
Vliegen, Jo	Speed Records in Network Flow Measurement on FPGA
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Wang, Kun	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
Wang, Lingli	Two-level MUX Design and Exploration in FPGA Routing Architecture A High-performance Open-channel Open-way NAND Flash Controller Architecture
Wang, Yao	Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Wang, Yun	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Wang, Zeke	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Weber, Nico	HALF: Holistic Auto Machine Learning for FPGAs
Wehn, Norbert	HALF: Holistic Auto Machine Learning for FPGAs
Wei, Tao	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
Wen, Fei	FPGA-based Hyrbid Memory Emulation System
Whatmough, Paul	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Wickerson, John	(Short Paper) Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining
Wildermann, Stefan	CHOICE – A Tunable PUF-Design for FPGAs
Willig, Michael	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
Wilton, Steve	MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Wong, Weng Fai	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Wu, Chen	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
Wu, Meiqing	Accelerating Continual Learning on Edge FPGA
Wulf, Cornelia	A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
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Xiao, Nong	Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs
Xu, Zhenyu	Minimal Overhead Optical Time-domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmabe Voltage Offset
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Yan, Shun	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Yang, Liwei	DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Ye, Tian	Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
Yin, Wenbo	A High-performance Open-channel Open-way NAND Flash Controller Architecture
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Zeng, Chenglong	*An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Zeng, Kai	Distributed Recommendation Inference on FPGA Clusters
Zgheib, Grace	Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
Zhang, Wei	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Zhao, Kun	Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Zhou, Chuteng	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
Zhou, Hao	Two-level MUX Design and Exploration in FPGA Routing Architecture
Zhou, Jingren	Distributed Recommendation Inference on FPGA Clusters
Zhu, Yu	Distributed Recommendation Inference on FPGA Clusters
Zhuang, Jinming	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
Ziener, Daniel	Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

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