ABSTRACT. Although some commercial EMC standards have existed for many years, the implementation of the European EMC Directive changed the standards’ landscape. In subsequent years, existing standards have continued to be developed and these have been complemented by new ones, focussed on particular industry sectors. In recent years, however, a significant challenge has been posed to the existing standards regime by the rapid advancement of technology, technology convergence and multifunction products.

This presentation will describe the evolution of commercial EMC standards from the early beginnings through to the latest developments that may form the blueprint for how standards are developed and applied in the future.

ABSTRACT. The paper presents a detailed study of the dynamic response of an Automatic Gain Control loop (AGC loop) exposed to pulsed radiofrequency interference. It is shown that the most significant effect is an increase of the RF output level of the AGC that is strongly dependent on the pulse repetition frequency, the effect being less pronounced as the repetition frequency increases. It is demonstrated that this is related to the transient response of the logarithmic amplifier, which can be controlled by decoupling capacitors.

ABSTRACT. Current sensors are usually protected against electromagnetic interference (EMI) by means of filters placed at the PCB level. The literature has plenty of solutions aimed at keeping EMI filters' attenuation as high as possible in the widest possible frequency range. However such filters are less effective than expected because of the parasitic elements introduced by interconnects. As a consequence, EMI can be propagated into ICs causing temporary or definitive operation failures. This paper points out the causes of EMI-induced errors in high-side current sensors based on low-offset chopper OTAs. Analyses presented in the paper are supported by direct power injection measurements carried out on a test chip.

ABSTRACT. This paper studies and compares the RF immunity of DC current regulators against electromagnetic interferences (EMIs). The effect of EMI on the performance of a classic topology is analyzed. It turns out, especially the regulators output is very sensitive against EMI since disturbance levels in the millivolt range cause serious malfunctions. Subsequently the paper introduces a structured approach to the design of EMI resistant regulators. RF immunity measurements on IC level (DPI) and on system level (BCI) proof the superior EMC performance of the resisting topologies over the classic regulator, while the electrical characteristics and the area of the circuits are the same. The circuits have been designed using a HV- BiCMOS technology for automotive applications.

ABSTRACT. This paper presents the analysis of effects and consequences of ESD on an operating integrated communication interface. We used a test structure for a differential bus module and observed its output signal behaviour under conducted ESD gun stress, to our knowledge for the first time. Measurements correlate to our simulations. 

ABSTRACT. Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.

This workshop proposes a global methodology using true transient co-simulation which combines three dimensional (3D) Electromagnetic (EM) analysis of the PCB and the package along with the chip power switching macro-modeling. To effectively design a complex system such as chip/package/board, it is imperative to use a co-design approach where different disciplines interact with each other such as Signal Integrity and timing analysis, Power Integrity, Power Distribution Network (PDN) extraction and noise analysis, EMC/EMI radiation analysis and finally thermal and stress analysis. CST STUDIO SUITE® offers a unique single user-interface to easily obtain the result of all these analysis in order to achieve a reliable design.

ABSTRACT. Near-field injection at silicon level is a promising method for various areas such as the analysis of radiated immunity to electromagnetic disturbances. Up to now, the research has been mainly focused at PCB level due to the resolution of the near-field probe. This paper presents first investigations of near-field injection on a Safe System Basis Chip at die level. The investigations are focused on one of the regulators included in this IC. The goal is to check if the Fail Safe Machine detects correctly the regulator failures during near-field injection. Moreover, simulations help to understand the failure mechanism.

ABSTRACT. A small-signal model of an automotive system-level bulk current injection (BCI) setup developed with a generalized accurate method shown in the previous publication [3] is verified on a case study with a demonstrator EUT module. The work utilizes an equivalent circuit modelling approach for the floating ungrounded EUT board and a macromodel for an active DUT IC. The simulation-based prediction of the BCI test results using an IC failure threshold and a small-signal simulation of RF levels at floating EUT module under BCI tests is shown. Due to high accuracy and detail of the BCI setup model, the prediction also shows very good correlation to real measurement data, both qualitatively and quantitatively, up to 1 GHz.

ABSTRACT. Because predicting undesired behaviors in IC (Integrated Circuit) due to conducted electromagnetic disturbances is necessary for front-loading the design process, immunity models are becoming more important to predict a malfunction at the design stage of electronic products. In this paper, the failure to function mechanism in a LDO (Low Dropout) voltage regulator is investigated from the aspect of the internal terminal in a circuit. Simulations confirm a relation between the internal reference voltage and the DC shift error at certain frequencies. Thus, monitoring the voltage or current at an internal terminal between functional blocks gives useful information about an IC model to predict immunity.

ABSTRACT. To evaluate the radiative immunity of an integrated circuit, we employ the IEC-standardized IC stripline method. In this paper, we provide an electromagnetic immunity analysis of the radiated electromagnetic noise coupling from an IC stripline to a ring voltage-controlled oscillator (VCO). We present the design of an IC stripline that meets the IEC 62132-8 standard, the test setup and the experimental results of the VCO test chip. The measurement shows that the radio frequency (RF) source from the IC stripline causes changes in the center frequency and output height. VCO output variations show that the design is relatively immune to radiated noise of the same frequency as the oscillator output, and the output frequency spectrum spreads out more with higher noise amplitude due to injection. The experiment shows that the IC stripline method is an effective solution for the radiated electromagnetic analysis of an IC.

ABSTRACT. The freeware IC-EMC is a windows-based software demonstrator which aims at simulating parasitic emission and susceptibility of integrated circuits. The demonstration proposed at EMC Compo 2015 illustrates the main features of the tool and recent IC case studies analyzed with IC-EMC, including a DSPIC processor, a Package-on-Package, and a Ethernet transceiver.

ABSTRACT. Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.

This workshop proposes a global methodology using true transient co-simulation which combines three dimensional (3D) Electromagnetic (EM) analysis of the PCB and the package along with the chip power switching macro-modeling. To effectively design a complex system such as chip/package/board, it is imperative to use a co-design approach where different disciplines interact with each other such as Signal Integrity and timing analysis, Power Integrity, Power Distribution Network (PDN) extraction and noise analysis, EMC/EMI radiation analysis and finally thermal and stress analysis. CST STUDIO SUITE® offers a unique single user-interface to easily obtain the result of all these analysis in order to achieve a reliable design.

ABSTRACT. In-band spurious tones of a LTE-class radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip was studied in order to evaluate the degree of noise suppression by means of soft magnetic thin film. A 2-μm-thick crossed anisotropy multilayered Co-Zr-Nb film was applied onto the passivation layer of TEG chip. The in-band spurious was suppressed by 10 dB while it had no influence upon wanted signal. A magnetic near field map measured in the 2.1 GHz range indicated several noise coupling paths on chip, which were compared with the chip layout design to estimate victim wires. EM simulation model in connection with circuit simulation is carefully constructed. RF control wirings were most responsible wires than other wires and air couplings. EM simulation predicted the magnetic film should suppress noise by the maximum of 33 dB while it was 10 dB experimentally because of Si substrate coupling and board coupling.

ABSTRACT. Simultaneous switching noise (SSN) is caused by the simultaneous switching of a group of I/O drivers, and is proportional to the total inductance and the rate of change of the switching current. This often leads to signal distortion and degradation of signal and power integrity of systems. Furthermore, with the continuously decreasing operating voltage, susceptibility to SSN keeps on increasing and it becomes increasingly challenging to achieve high performance interfaces.  Therefore, it is highly important to perform SSN analysis in order to accurately investigate the noise and timing margin of the devices under test; hence, it is important to know the exact amount of switching current drawn by the ICs. In this paper, we propose TSV-based current probing structure using magnetic coupling, named TSV-based Current Probe (TCP). By capturing the magnetic flux induced by the injected current and processing it through a series of reconstruction steps, we can obtain the original current waveform of interest. Through a series of simulations in frequency and time domains, we verify the performance of the proposed probing structure, TCP. Lastly, TCP is fabricated using TSV fabrication techniques and measured for experimental verification.

ABSTRACT. Transient disturbance signals are getting more and more attention lately (e.g. in the automotive industry). Electromagnetic compatibility (EMC) at IC level so far focused on continuous wave (CW) disturbances and how to deal with them, but transient phenomena were not thoroughly studied yet. In this exploratory paper, we perform a case study (based on a basic current mirror) in order to reveal the effects of transient disturbances (as compared to CW ones) and to determine what IC design techniques could be used to deal with them.

ABSTRACT. A 3rd order lumped element circuit for the simulation of the JEDEC JS-001-2014 HBM ESD pulse is proposed. The resulting current pulse is analytically computed with a state space model of the circuit. For the purpose of verification a computer algebra system is used, solving and checking the model if it generates a current pulse which fulfils the requirements. The values of the voltage pulse, resistor, inductor and capacitor can be changed dynamically, resulting in an instant check against the standard which is also visualised by a plot. Finally the results are compared against numerical simulation in SPICE.

ABSTRACT. This paper deals with the characterization of the immunity of integrated circuits (ICs) by means of their susceptibility to conducted radio frequency (RF) electromagnetic interferences (EMI). It describes and analyses a framework to perform such characterization at wafer level, highlighting the benefits that are reaped from it and the problems that can be faced during the test bench setup, giving some possible solutions.

ABSTRACT. with constraints for high-level integration of electronics, new EMC behaviors have to be considered to prevent real electromagnetic compliance. Especially, in embedded and on-board device's context, environmental temperature has an influence on the circuit behavior and EMC figures. This paper deals with susceptibility studies combined with temperature effects on electronic devices used to control power and transmissions. Specific dual thermal-electromagnetic test set-up developed for this are presented. Main results of an experimental campaign on digital PCB dedicated for generation of Pulse Width Modulation (PWM) patterns are presented. Temperature dependant susceptibility and sensitivity of the PWM parameters are compared and analyzed.

ABSTRACT. This paper introduces a new Direct Power Injection (DPI) set-up used to characterize the conducted immunity of integrated circuits (IC) with differential inputs. It allows injecting common-mode, differential-mode signals or any combination of both. For a given kind of injection, it is necessary to calculate power and phase-shift at generators. To do so, an analytic model is developed based on S-parameters of all blocks involved in the set-up including the IC. This model is validated by simulation under PSpice and by measurement in [1 MHz – 800 MHz] band for pure common-mode and pure differential-mode injections. With this set-up, IC immunity can be characterized as functions of common-mode and differential-mode voltages versus frequency.

ABSTRACT. System-in-package (SiP) encloses multiple dies in a single package which is much sensitive to electromagnetic interference. This paper presents computational analysis of shielding performance by modelling, simulation and optimization of a radio frequency integrated circuit (RFIC) in SiP using a self-developed virtual electromagnetic compatibility (VEMC) system. The system is designed and proved for computational electromagnetics needs in high performance computation and visualization. Multi-objective optimisation in package thickness, material conductivity, number and order of shielding derives an optimal shielding effectiveness for the discussed package.

ABSTRACT. With substantial progress in Internet of things (IoT), new challenges of EMI on IoT (IoT-EMI) measurement have emerged. The IoT-EMI behaviors are complex and dependent on the target’s interactions between hardware and software A systematic method for IoT-EMI measurement should be developed. However, the characteristics of IoT-EMI are digitally-controlled, time-varying, and software-dependent and make the IoT-EMI measurements difficult by conventional method. This paper proposes a time-domain measurement method for such issue. This method uses a ‘timestamp’ by SW/HW-co-measurement strategy to analysis IoT-EMI behaviors. From the measurement result, the long-term measurements are comparable to the conventional SA measurements. And the software-related IoT-EMI results show tremendous differences – about 5-50 dBuV differences among different application programs are observed. The software-dependent IoT-EMI behaviors are firstly observed and published.

ABSTRACT. This paper proposes a radio-frequency interference (RFI) evaluation method for flexible flat cables (FFCs), which are commonly employed for high-speed signal transmission in modern mobile devices and become a major path of noise coupling to antennas. The noise coupled from differential-mode and common-mode signals flowing through FFCs is obtained in terms of transfer functions based on S-parameter measurement. Considering the source power from a driver IC on the main board sent to the FFCs, the noise power at the antenna was calculated to evaluate the noise coupling through the FFCs based on a criterion of RFI noise power received at an antenna port. To measure the coupled noise in terms of transfer function, a dedicated evaluation board is designed and fabricated. Several low-voltage differential signaling (LVDS) FFCs used in a real tablet were evaluated based on the proposed method and validated by experimental measurement on RFI noise power at Wi-Fi antenna port using both the evaluation board and the real tablet. A good correlation was achieved between them.

ABSTRACT. Near-field injection is a promising method for the analysis of the susceptibility of electronic boards and circuits. The resulting immunity map provides a precise localization of the sensitive area to electromagnetic disturbances. A major requirement is the spatial resolution of the immunity map, which depends on the size of the injection probe and the separation distance between the probe and the device under test. This paper aims at proposing a post-processing method to enhance the spatial resolution of immunity map and validating it on case studies at board and integrated circuit levels.

ABSTRACT. In this paper, the Transmission Line Matrix (TLM) method is used to study the electro-thermal performance degradation in RF LDMOS (Radio Frequency - Laterally Diffused Metal Oxide Semiconductor) transistors, through Thermal Cycling Test (TCT), as the temperature is a crucial parameter in RF devices. A hybrid approach is presented, which combines the modelling of thermal diffusion and electric effects within a two dimensional TLM model to observe the device behaviour after simulated ageing, through including the ageing loop in a unified solver. Two sets of test results are compared with published data in order to verify the performance of the proposed hybrid solver. The work shows the suitability of using the TLM to model ageing phenomenon in MOS devices

ABSTRACT. Apart from ESD tests at system level, e.g. according to IEC 61000-4-2, the investigation of the EMC immunity of individual ICs is becoming increasingly important: an ESD sensitive IC could cause problems in subsequent system level tests when in use. Knowing in advance what to expect from an IC can help save time and money in the design process. An appropriate component level test bench is therefore required. Using standard ESD generators (system level test methods) for component level tests can lead to unexpected results. This paper describes problems that can arise when using standard ESD generators in a customised test set-up whereby a microcontroller is used as a DUT (the tested IC) for demonstration purposes.