ABSTRACT. Radiation characteristics of a loop antenna, small compared to the wavelength and placed centrally above a perforated finite image plane, are presented. Holes in the image plane typically occur in a multilayer printed circuit boards (PCBs) when vias pass through the second layer which serves as a reflector. A 3D finite element method (FEM) electromagnetic (EM) simulation of a System-in-Package (SiP) synchronous buck converter shows a significant impact of the holes on the characteristics of the converter. A parametric analysis of the impact of the number and radius of holes on the radiated characteristics and on the inductance of a small loop antenna above perforated image plane is performed by 3D FEM EM simulations. Guidelines for a design of multilayer PCBs for magnetically driven sources, such as DC-DC converters, are deduced.

ABSTRACT. As the electromagnetic compatibility of IC products takes on greater significance for competitiveness, IC manufactur- ers are increasingly interested in evaluating the EMC properties as soon as during the very first design phase without the need of prototypes. There are a number of approaches to predict radiated emissions of automotive components as defined in the CIPSR25 standard. One can conclude that none of them is suitable for continuous use by the circuit designer because they either need a manufactured prototype and a lab engineer, or lots of simulation time and resources. This paper presents the generation and use of a simulation model which can be easily implemented in the design environment used by the designer (e.g. Cadence Virtuoso) and does not notably increase the simulation time. The transient output data is post-processed with a Matlab script emulating an EMI test receiver.

ABSTRACT. This paper deals with the “in band” and “out band” rectification of a Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s) device and proposes a semi-empirical model to predict the rectification effect in all transistor regions. The modeling method is based on two variables Taylor series expansion of Id(Vgs,VDS) which shows a modification in drain current due to a gate Radio-Frequency (RF) voltage. This modification depends on the transconductance and conductance derivatives. When the transistor operates in the non-saturation and linear region the conductance becomes an important nonlinear source. However, it can be neglected in the saturation region of the MOSFET.

ABSTRACT. In this paper, the signal integrity (SI) and Electromagnetic Compatibility (EMC) performance of System-On-Chip (SoC) and stacked memory using Package-On-Package (PoP) technology is investigated. The reconfiguration of the IC-EMC software platform to PoP is described. From an existing 2D assembly using a discrete 65-nm SoC product, the benefits of PoP integration using a next-generation (NG) 28-nm product with stacked memory are analyzed, based on simulation and predictive analysis performed using IC-EMC software platform.

ABSTRACT. Modern PCB Designs for automotive, wearable, and mobile applications must validate the stability of the power delivery network early in the design phase. Increasing bandwidths of integrated interfaces of Memory and FPGAs requires early estimation of radiation behaviour of the printed circuit board and optimization to meet specified compliance limits. In order to meet these targets, engineers are finding great success in adapting a design process that provides EMI insight early in the design stage. Such an EMI Aware Design process is achieved by using the same electromagnetic tools from ANSYS that are used for power and signal integrity design. Using ANSYS's electromagnetic suite engineers are able to detect and eliminate potential EMI sources while they are optimizing their signal channels and power delivery networks. With this flow, the impact of the PCBs self resonances, the quality of the decoupling capacitors, and decap placement can be analysed. Using Near- and Far-Field computation algorithms, the radiation pattern of the PCB can be analysed and optimized based on number, placement and value of decoupling caps.

ABSTRACT. This paper deals with the susceptibility to radio frequency interference of smart power integrated circuits. A method to perform simulations aimed at evaluating the performance of subcircuits included in a more complex IC is presented. Such a method is used in this work to investigate the behaviour of a current sensor included into an high-side power switch, when performing the direct power injection test.

ABSTRACT. Through silicon via (TSV) has been extensively highlighted as the key solution for small form factor wide bandwidth, and low power consumption with compactly integrating multiple chips. Despite the many advantages of TSV based 3-dimensional integrated circuit (3D IC), there are several challenges to be overcome such as noise coupling, fabrication process limits, and failure issues. In this paper, we proposed shielding structures for TSV to active circuit noise coupling in 3D IC. The proposed structures can capture TSV substrate noise by blocking the noise paths to active circuit, LC-VCO in this study. The noise suppression mechanisms are analyzed by the noise coupling coefficient in frequency-domain obtained by 3D electromagnetic simulation. Various shielding structures are investigated and compared with regard to sensitivity of active circuit, such as phase noise of LC-VCO.

ABSTRACT. A new international standard proposal (IEC 62433-2 Edition 2.0) is in progress. The main purpose of the standard is to provide an Integrated Circuit Emission Model – Conducted Emission (ICEM-CE) along with a data exchange format. It is known that the existing ICEM-CE information is closely linked to the supplier of the model or simulation software used to generate the model information, rendering extremely difficult its exchange between suppliers, customers, EDA tool vendors, academics, etc. This paper describes a universal exchange format for ICEM-CE. The format is based on the well-known eXtensible Markup Language format, which is both machine and human readable. As an illustrative example, it is applied on an Atmega88 microcontroller: the model is extracted by the manufacturer, Atmel, and is exchanged with an academic partner, INSA, and an industrial partner, Valeo. The exchange proves fruitful and the model was easily deployable to predict conducted emission noise.

ABSTRACT. An interchangeable black-box model of an integrated circuit block for time-domain simulations of the direct power injection (DPI) immunity test is presented. An artificial neural network implemented as a Verilog A module is used to build a model of a bandgap reference circuit sub-block. Being a part of a larger schematic of interconnected circuit blocks, the model is able to correctly load the transistor-level block in the previous stage. The simulation time for the transient analysis is significantly improved compared to the transistor-level models, and the time-to-steady-state of the model is negligible. The accuracy of the model is comparable to the state-of-the-art black-box modelling approaches. The model is very practical for obtaining the EMC behaviour of complex integrated circuits at design-time.

ABSTRACT. This paper deals with the study and the modelling of temperature/humidity effects on conducted immunity of electronic circuits. We focus first on experimental measurements using DPI (Direct Power Injection) test bench for the characterization of conducted immunity associated to an air conditioner that allows warming up the circuit locally. It is shown that the increase of temperature seems to decrease the sensibility of the tested circuit. Secondly the behavioural immunity model (ICIM-CI), developed in VHDL-AMS and taking into account temperature effects is presented. The model is finally validated by comparison with measurements. In a second time, the DPI test bench is used with a climatic chamber to study the effect of humidity on the immunity caracteristics of electronic circuits. It is shown that no significant effect is observed, at least for low disturbance power.

ABSTRACT. “First pass design success” is critical in achieving time-to-market for today’s consumer electronics systems. Power noise and associated reliability issues often come up late in a design cycle and threaten product release dates. ANSYS will present how their Chip-Package-System workflow allows for comprehensive modelling, co-analysis and optimisation of today’s high performance, low power electronic systems from the IC level at advanced process nodes including the effects of and on the package, board and system. Using the ANSYS tool suite, engineers are able to run analysis and optimization of Voltage Drop, Electromigration, Electrostatic Discharge and Electromagnetic Interference taking the entire system into account. This streamlined flow enables early simulation and optimization making the design process more efficient and cost-effective while ensuring performance of the system prior to production.