ABSTRACT. Due to their high efficiency compared to conventional Class AB amplifiers Class D audio amplifiers have increasingly became the amplifier of choice especially for low power applications such as portable electronics. However, Class D amplifiers are still one of the major sources of the electromagnetic emission of the electronic products in which they are used. In this paper the benefits of using spread spectrum techniques in order to reduce the emission of Class D audio amplifiers is highlighted. Based on the measurements of a 10W Mono Class D speaker amplifier, that allows to be synchronized to an external clock, it is shown how spread spectrum parameters like deviation, modulation frequency and modulation signal can be optimized in order to maximize the reduction of the emission.

ABSTRACT. This paper presents the dead-time variation analysis and far-field radiation estimation of a DC/DC converter. The critical factors influencing the dead-time variation are identified and their statistical distributions are defined. The statistical distribution of the MOSFET parasitic capacitances is optimized to match the values obtained by measurements. The packaging process variation together with the variation of the printed circuit board properties are identified and transferred into circuit simulator by the response surface methodology (RSM). The RSM models together with the simplified synchronous buck DC/DC converter model is implemented in circuit simulator and Monte Carlo simulation is performed. The dead-time variation is extracted from Monte Carlo simulation results and most significant sources of variation are identified. The switching current extracted from the simulation results is used to estimate variation of the far-field radiation.

ABSTRACT. This paper presents a novel CAN transceiver based on a highly-digitized architecture designed and fabricated in 0.14μm high-voltage SOI CMOS. This advanced BCD process allows the implementation of this innovative architecture which combines digital and high-voltage analog circuits. Hence, the output stage can be split in multiple unit cells successively enabled or disabled by a shift register. It also allows an advantageous implementation of a dual-clock CAN receiver that combines an architecture optimized for high EMI with a low-power mode where a low-frequency clock is used to reduce the power consumption. EMC performance was evaluated according to automotive industry standards. It shows excellent EME and EMI compliance to car manufacturer requirements without using a common-mode choke.

ABSTRACT. There is a growing need for motor drives with improved EMC in various automotive and industrial applications. An often referenced approach to reduce EME is to change the shape of the switching signal to reduce the EMI caused by the voltage and current transitions. This requires very precise gate control of the power MOSFET to achive better switching behaviour and lower EME without a major increase in switching losses. In order to find an optimal trade-off, this work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns. With this driver, measurements with different gate current profiles were taken. The di/dt transition was confirmed to be as important as the dv/dt transition in the power MOSFET. As a result of the improved switching behavior the emissions were reduced by up to 20dB between 7MHz and 60MHz with a switching loss that is 52% lower than with a constantly low gate current.

ABSTRACT. This paper deals with the conducted immunity of SPI EEPROM memories. The design and implementation of a wideband radio frequency-baseband multiplexer are described. This multiplexer makes it possible to superimpose radio frequency noise to a functional baseband signal with controlled and repeatable transfer characteristics. The baseband path has a measured DC-380MHz bandwidth, while the radio frequency path (up to 1W) has a 150kHz-5GHz bandwidth. This multiplexer is used to compare the conducted immunity of functional and non-functional pins of EEPROM memories with a single measurement set-up.

ABSTRACT. Electromagnetic (EM) injection experiments require an accurate and quantitative knowledge of the voltage effectively coupled to a target line or circuit in order to predict disruptive behavior or sensitivity of digital IC circuits to EM threats. To answer this question we derive here a complete quantitative model of the coupling of our magnetic probe to a microstrip line. The novelty of this model is to consider the coupling by analogy with a transformer and then to deduce the corresponding mutual inductance as a function of probe to target relative positions. Its inputs are S-parameter measurements of the actual probe coupled to a 50 ohms microstrip line and its output is an electric equivalent circuit that can be implemented in any circuit simulator. Validity of the model extends up to GHz frequencies.

ABSTRACT. In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. The presence of low power and high voltage devices in Smart Power ICs cause parasitic substrate interaction between switched power stages and sensitive analog blocks. Nowadays this is the major cause of failure of Smart Power ICs inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this type of interaction expressed as an injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures. This paper presents a study of bandgap failure issues due to the substrate coupling induced by high power parts of the circuit which can activate parasitic bipolar structures inside the substrate of Smart Power ICs.

ABSTRACT. This paper discusses a countermeasure against Correlation Power Analysis (CPA), which can be relatively inexpensively and easily implemented. CPA calculates the correlation value between the transient current waveforms and hypothetical current values under the assumption that the specific process that leaks the secret key information is always performed after a certain time from the time when the cryptographic IC starts performing encryption or decryption and recovers the secret key. Therefore, we consider the possibility of randomizing the time when a cryptographic IC runs the process where the secret key information is leaked to suppress the leakage of side-channel information available in recovering the secret key. In this paper, we propose a method of changing the clock frequencies for each encryption or decryption to randomize the time.

ABSTRACT. This paper describes a LIN (Local Interconnect Network) Transmitter designed in a BCD HV technology. The key design target is to comply with EMI (electromagnetic interference) specification limits. The two main aspects are low EME (electromagnetic emission) and sufficient immunity against RF disturbance. A gate driver is proposed which uses a certain current summation network for lowering the slew rate on the one hand and being reliable against radio frequency (RF) disturbances within the automotive environment on the other hand. Nowadays the low cost single wire LIN Bus is used for establishing communication between sensors, actuators and other components.

ABSTRACT. Inside the car, all integrated circuits “IC” have to be optimized to survive against severe external aggressions. The noise generated by each activity inside each IC must be low enough, to not disturb the environment. As known nowadays, DC-DC converters can significantly impact the Electromagnetic Compatibility “EMC” performances, and mainly the emission ones. Unfortunately, simulation with linear models like ICEM or IBIS models [1, 2] remains very challenging for integrated analogue products due to the high number of parameters, plenty of possible applications and the extent of the frequency domain where the integrated circuit must be compliant. A paper describes an analytical approach to highlight the main contributors to the high frequency noise generated by switching activity in Buck converters [3]. This approach is then employed to reduce Conducted Emission “CE” performance using multiphase interleaved Buck converters and to highlight benefits of increasing the number of phases in improving the emission profile.

ABSTRACT. This paper deals with low offset operational amplifiers. It shows an innovative approach to design an operational amplifier (OpAMP) which combines two different techniques that enables to handle both the technological offset and the radio frequency interference (RFI) induced offset.

ABSTRACT. A simulation methodology to predict and mitigate interferences between different subsystems in complex mixed-signal system-on-chip ICs at the early stages of a design project is presented. Different aspects of the analysis flow and the abstraction levels of the models are discussed. The impact of the floorplan and design choices on circuit performance and the relative contribution of different coupling mechanisms are shown on a number of examples. Special attention is paid to on-chip and package coupling effects. The methodology has been validated with silicon measurements and has been successfully applied in the design process of NXP products.

ABSTRACT. The use of Real-Time Operating System (RTOS) became a mandatory condition to design safety-critical real-time embedded systems based on multicore processors. At the same time, these systems are becoming more and more sensitive to transient faults originated from a large spectrum of noisy sources such as conducted and radiated Electromagnetic Interference (EMI). Therefore, the system’s reliability degrades. In this work, we present a hardware-based infrastructure intellectual property (I-IP) core able to monitor the RTOS’ activity in a multicore processor system-on-chip (MPSoC). The final goal is to detect faults that corrupt the task scheduling process in embedded systems based on preemptive RTOS. The I-IP core, namely RTOS-Watchdog (RTOS-WD), was described in VHDL and is connected to the address busses between the cores and their local iCache memories. A case-study based on a MPSoC running different test programs under the control of a typical preemptive RTOS was implemented and exposed to conducted EMI. The obtained results demonstrate that the proposed approach provides higher fault coverage when compared to the native fault detection mechanisms embedded in the kernel of the RTOS.

ABSTRACT. To be compliant with electromagnetic compatibility standards, integrated circuits such as microcontrollers have to be robust to fast transient burst tests. Because of high voltage and fast transient voltage variations used no measurement is possible during the stress. Lack of information make the debug of a product a real challenge. The objective of this work is to provide a measurement method which permits to have more information on the stress propagation on the power supply network. The methodology applied here on fast transient burst test could be extended to other kind of stress on power supply.

ABSTRACT. This paper discusses the shielding performance or shielding effectiveness of a board-level shield in function of its bonding method. Improved shielding performance at board-level in order to harden integrated circuits against unintentional and intentional electromagnetic interference, and this under harsh environmental conditions, is getting more and more important to achieve the desired levels of functional performance and operational reliability despite an ever more aggressive electromagnetic environment. High levels of operational reliability are increasingly  being required to help control functional safety or other risks. As a board-level shield on its own only provides 5 of the 6 required walls to form a complete Faraday Cage, its overall shielding performance depends heavily on the way it is bonded to the printed circuit board’s ground plane. It is shown by fullwave simulations that the shielding effectiveness can improve by more than 40 dB when bonded with the waveguide-below-cutoff principle compared to a classic perimeter bond of a single row of vias. And this even if the waveguides-below-cutoff are formed by rows of vias. Finally, the paper stresses the influence that internal resonances of the board-level shield have on its shielding effectiveness.

ABSTRACT. System Efficient ESD Design (SEED) requires dynamic response data from the devices and circuitry used along the protection chain, typically from the point of entry at the PCB boundary i.e. connector up to the circuits on-chip to be protected. In-between this path there may be external ESD protection i.e. voltage clamping with parasitic layout effects, interconnect path delay with specific transmission line properties, package design, on-chip protection design with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being non-powered or powered on or the response parameters are affected by the presence of RF e.g. with smart phone and wireless appliances. In this 1st paper a proposal to gather the multi-dimensional response parameters will be given together with the rationales. At the end of the paper some examples will be presented. Future parts will contain data analysis, model building and model validation.

ABSTRACT. In the presented paper we examine and compare different adder structures for their EMC behavior. On the one hand the analysis is carried out for different topologies as Ripple Carry Adder and Kogge Stone Adder. And on the other hand these topologies are realized in different logic styles as standard CMOS, complementary pass transistor logic, buffered NMOS pass transistor and complementary buffered NMOS pass transistor logic. All these variations are compared over di/dt, power consumption, speed / performance and transistor count. Additionally a new topology for the Kogge Stone Adder is introduced.

ABSTRACT. This paper presents the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate in order to build up a model to be used in simulating EMC performances — both emission (EME) and immunity (EMI) — and to be able to predict early in advance, before silicon fabrication, EME-EMI characteristics. The chip is realized in 40 nm CMOS technology, the one used for the realization of automotive microcontroller. Four versions of the chip are presented and some measurements are shown. This first paper focuses on emissions aspects, even if the schematic architecture and layout has been developed to cover immunity phenomenon too. To understand the role played by the silicon substrate as propagation medium (noise internally generated to outside or to convey the external environment interferences into the silicon circuitries), the ESD pin protections have been removed on two versions of the test chip. The same electrical architecture is also proposed in different layout designs: with and without the Deep N-Well (DNW) implant allowing isolation of pwell substrates, to evaluate the benefit of this process technique. Previous work is discussed, and new hypotheses and emission measurements are shown. This work is focused on the basic version of the test chip, without DNW and ESD protection, to highlight noise propagation due to the substrate only, without intervention of different physical structures.
 

ABSTRACT. The electromagnetic interference (EMI) generated from the DC-DC buck converter effects the performance of integrated circuits which receive power supply from the buck converter. In this paper, the EMI reduction techniques of DC-DC buck converter are presented. The damping resistor is applied to reduce the output noise of the buck converter. In time domain, this damping resistor technique reduces the output noise of the buck converter significantly but is not effective in reducing high frequency noise components. To resolve this issue, PCB design is modified to contain separate planes for input, output, switching, and ground ports. The TEM-cell, measurement results show that with this modification in addition to the damping resistor, the EMI is significantly reduced over a wide range frequency up to 1GHz.

ABSTRACT. In very-large-scale-integration (VLSI), arbitrary structure of interconnections leads to unpredictable parasitic capacitance that generates EMC issues. This paper investigates an EMC modelling and optimization method in calculating interconnect capacitance of VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II).