DSD2022: EUROMICRO CONFERENCE ON DIGITAL SYSTEMS DESIGN 2022
TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

A
AAL systems
accelerator
activation sparsification
adaptive fault tolerance
adaptive redundancy
Adaptive Routing
Adders
Adversarial Attacks
Adversarial bit-flip attack
Air congestion
Allan variance
analysis
Anomaly Detection
Application Mapping
Approximate adder
Approximate Adders
Approximate and Exact MPSoC
Approximate computing
Approximate multiplier
Approximate square root
Approximation Computing
Architecture exploration of RRAM crossbars
Area efficient
Arithmetic Operator Design
ARM
Artificial intelligence
ASIC
Assertion Minimization
Assertion Mining
Assertion-Based Verification
Asynchronous
attack generation
attack simulation
attention mechanism
audio data
automated circuit design
Automotive
automotive cyber-physical systems
Autonomous Driving
B
Backdooring
Bayesian inference
belief propagation decoding (BPD)
bfs
BIKE
Binary
Binary Decision Diagrams
Binary nonlinear codes
bit manipulation
blood perfusion
Body-Biasing
boot
bootROM
brain tumor
breadth-first search
C
cancer
Cancer diagnosis
Cervical cancer
Cervical Intraepithelial Neoplasia (CIN)
CFI
Chip Multiprocessors
cipher
Circuit Synthesis
Clustering
CMPs
CNN accelerator
code generation
code-based cryptography
Cognitive system
Coherency
collective communication
Communication
Compression
computation efficiency
Computer Aided Engineering
computer architecture
computer vision
computing array
Condition Monitoring
congestion mechanism
continuous system engineering
Contrast agents
Control-flow integrity
Controlling
Convolutional Neural Network
Convolutional Neural Networks (CNNs)
convolutional-neural-networks
Coordinate rotation digital computer (CORDIC)
Coordinate-based Scoring
Countermeasures
CPPS development
CPU-GPU tandem
cryptography
CV
Cyber Physical Systems (CPS)
cybersecurity
D
Data representation in RRAM crossbars
Data-Intensive Application
Database Management
datacenter
Decision Tree
decomposition
deep learning
Deep Neural Network
Deep neural network optimisation
Deep Neural Networks (DNN)
deep-learning
Design for testability
Design Space Exploration
Directory
Disassembly
Distributed Cyber-Physical Systems
Distributed Learning
Distributed Simulation
Distributed system sustainability
domain specific accelerators
Drones
DSP delay lines
DVS
Dynamic Dependability Management
Dynamic Partial Reconfiguration
Dynamic Risk Management
dynamic vision sensor
E
Earliest Deadline First Scheduling
Early-exit
EDF
edge AI
edge computing
edge detection
edge devices
Efficient programming of RRAM crossbars
efficient training
Elderly Fall Detection
Electronic Design Automation
EM analysis
embedded deep learning
Embedded Systems
Energy
energy efficiency
energy reduction
error metrics
ESL
EUREKA
event camera
Event-Driven Programming
evolutionary algorithm
evolutionary algorithms
Exact Synthesis
exergames
exposed datapath
F
fall prevention
Fault Attack
Fault detection
fault injection
Fault injection attack
fault model
Fault Prediction
Fault Tolerance
Fault tolerant systems
Fault Tree Analysis
Federated Learning
FIA
Field Programmable Gate Array (FPGA)
filtering
Fixed Priority Scheduling
Flight Safety
Formal methods
Formal Methods in System Design
Formal Verification
FPGA
FPGA SoCs
FPGAs
FPGAs in the Cloud
Free-choice Petri net
G
Gait analysis
Geant4
glioblastoma
GoodBrother
GPU
graph
graph processing
Graph theory
grid search
Guessing Entropy
H
Hamming Weight Leakage Model
Hardware
Hardware Acceleration
Hardware Accelerator
hardware accelerators
hardware and software redundancy
Hardware description language (HDL)
hardware design
hardware security
hardware security protocols
hardware software co-design
Hardware Verification
hardware-aware neural architecture search
Hardware/Software Co-Design
HDR enhancement
Health-condition
hemoglobin
Heterogeneous Embedded Systems
Heterogeneous Multiprocessor System-on-Chip
Heterogeneous Platforms
Heterogeneous systems
Heterogeneous virtualization
Hierarchical systems
High performance
High-Level Synthesis
histology
HLS
HPC
HUD
Human Activity Recognition
HW/SW codesign
hyperparameter
hyperspectral
hyperspectral images
Hyperspectral imaging
Hyperspectral imaging instrumentation
I
IC trust
IIRA
image processing
Image reconstruction
In vitro testbed
in-memory computing
Industry 4.0
Inference Latency
InfiniBand
Integer Linear Programming
Intelligent Totems
Interconnect
interconnection network
Internet of Things
IP Cores
IP obfuscation
IP protection
ISE
ITEA
J
jitter
junction trees
K
k-red
L
large model inference
lattice-based cryptography
Leakage Assessment
LiDAR
LiM-HDL
linear regression model
LLVM
load cell
Logic implementation with RRAM crossbars
Logistic Regression
Look-up-Table
LoRaWAN
low error
Low Power
low-cost
Low-dose Sparse Scanning
Low-Latency Ethernet
low-power design
LSTM
LWE/LWR-based KEM
M
Machine Learning
Majorization
Manycores
Masking
massively parallel computers
Matrix-Vector-Multiplication (MVM)
MEDA biochip
medical hyperspectral imaging
Memristor
memristor crossbar
MEMS mirror
message passing
Methodology development
microfluidic biochip
microscopy
Minimum clique cover problem
Mixed Criticality Systems
Mixed-Criticality
Mixed-criticality Systems
mixing
ML frameworks
mobile devices
mobile platform
mobilenet
Model Inference
Model-based analysis
modeling
Monitoring
Monte Carlo Simulation
MRI
Multi-Processor System-on-Chip (MPSoC)
Multi-Value CiM
Multicore processing
multilevel modelling
Multiplier
multispectral imaging
multivariate quadratic
N
Network-on-Chip
Neural Network
Neural network accelerators
Neural Networks
Neural processing unit
neuromoprhic
noise models
nonlinear mixing models
NTV
Number Systems
number theoretic transform
O
Object Detection
On-Chip Inference
open source hardware
open-source
operating system
Operational Design Domain
optical filters
optical imaging
optimization
P
PAIG synthesis
PAIG technology mapping
parallel execution
partial evaluation
Partial Reconfiguration
Pathology
PDES
perception architecture design
Perception System
Performance Modeling
personalized healthcare
Petri net
phase noise
PHM
Pipelines
platoon
PLiM
Pointer analysis
polar codes
polymorphic electronics
polymorphic gates
Posit Arithmetic
Position Awareness
posits
Post-Quantum
post-quantum cryptography
power consumption
Power efficient
Privacy preserving smart metering streaming
privacy-aware applications
probabilistic graphical models
Process in Memory
Processing-in-Memory
Processor
processor architecture
profiling
pseudo-Boolean optimization
Pseudo-exhaustive testing
public-key cryptography
Q
QC-MDPC codes
QDI
QoS
Quantization
Quantum computing
R
Radar
RAMI4.0
random forest
random search
Real-time
Real-time Analysis
Real-Time Operating Systems
Real-time systems
Real-time Tasks
Reconfigurable Crossbar
Reconfigurable Hardware
Reduced instruction set architecture
Reduced Instruction Set Computing
Reference architectures
reflectance calibration
Reliability
Reliability engineering
Remaining Useful Life
ReRAM
Research project
Resource Elasticity
Return-oriented programming
reverse engineering
Reverse-Engineering
ring oscillator
RISC-V
RISCV
Robot Operating System (ROS)
Round Robin Scheduling
routing ground holding
RRAM
RRAM crossbars
Runtime Monitoring
S
Saber KEM
Safety-Critical Systems
sample preparation
SAT
scalability
Scanning Electron Microscopy
Schedulability
Scheduler Synthesis
Scheduling
Schur Concavity
Secure communication
Security
security requirements
Sensing
Sentient spaces
sequential based-model optimization
Side channel
Side-channel
Side-Channel Analysis
side-channel attack
signal processing systems
simulation
simulator
skin cancer
SLIC
Small volume
smart floor
Smart grid privacy
sneak path
SNN
SoC
software product lines
software quality
software variants
Spatial Isolation
spiking
SRAM
STT-MRAM
Substitution Box
Success Rate
super-resolution
Superpixel
support vector machine
Support Vector Regression
surrogate model
synthesis
System architecture
system composability
system on chip
System-on-Chip
SystemC TLM
systems security
Systolic array
systolic arrays
T
Task Allocation
Task Scheduling
Telemetry
TensorFlow eager execution
Ternary Reversible Circuits
Test vector compression technique
theory of regions
tile artifact
time-predictable computer architecture
Time-to-digital converter (TDC)
Timing predictability
TLS
Trace Encoder
Traffic Management
Traffic Sign Recognition
Transition system
True random number generator
TTA
U
UAV
unmixing
Uppaal
Urban Air Mobility
V
validation
variable-length instruction set
vector instructions
verification
video data
vision processor
Vision Transformers
Vitis AI
W
Watermarking
Wave Union Launcher
WCHB
Workload Dynamism
Workload Modeling
Worst-case Analysis
X
Xtensa
Y
Yolo
Z
zedboard
Zynq UltraScale+ MPSoC