DSD2022: EUROMICRO CONFERENCE ON DIGITAL SYSTEMS DESIGN 2022

This page contains an index consisting of author-provided keywords.

A
AAL systems	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
accelerator	Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber
activation sparsification	ARTS: An adaptive regularization training schedule for activation sparsity exploration
adaptive fault tolerance	A holistic hardware-software approach for fault-aware embedded systems
adaptive redundancy	A holistic hardware-software approach for fault-aware embedded systems
Adaptive Routing	Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
Adders	Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the Best?
Adversarial Attacks	Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach
Adversarial bit-flip attack	Blind Data Adversarial Bit-flip Attack against Deep Neural Networks
Air congestion	A resolution method in case of air congestion: rerouting and/or ground holding approach
Allan variance	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
analysis	Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
Anomaly Detection	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
Application Mapping	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform
Approximate adder	A Majority-based Approximate Adder for FPGAs
Approximate Adders	Polynomial Formal Verification of Approximate Adders
Approximate and Exact MPSoC	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform
Approximate Computing	ESAS: Exponent Series based Approximate Square Root Design EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML A Majority-based Approximate Adder for FPGAs Designing Approximate Arithmetic Circuits with Combined Error Constraints
Approximate multiplier	RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
Approximate square root	ESAS: Exponent Series based Approximate Square Root Design
Approximation Computing	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
Architecture exploration of RRAM crossbars	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Area efficient	An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
Arithmetic Operator Design	PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML
ARM	Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
artificial intelligence	Partial Evaluation in Junction Trees Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations
ASIC	Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology A Resilient System Design to Boot a RISC-V MPSoC
Assertion Minimization	IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets
Assertion Mining	IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets
Assertion-Based Verification	IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets
Asynchronous	Towards Resilient QDI Pipeline Implementations
attack generation	A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks
attack simulation	A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks
attention mechanism	Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention
audio data	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
automated circuit design	Designing Approximate Arithmetic Circuits with Combined Error Constraints
Automotive	Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms
automotive cyber-physical systems	Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical Systems
Autonomous Driving	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
B
Backdooring	TextBack: Watermarking Text Classifiers using Backdooring
Bayesian inference	Partial Evaluation in Junction Trees
belief propagation decoding (BPD)	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
bfs	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
BIKE	FPGA implementation of BIKE for quantum-resistant TLS
Binary	Quantization: how far should we go?
Binary Decision Diagrams	Polynomial Formal Verification of Approximate Adders
Binary nonlinear codes	Nonlinear Compression Block Codes Search Strategy
bit manipulation	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment
blood perfusion	Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
Body-Biasing	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
boot	A Resilient System Design to Boot a RISC-V MPSoC
bootROM	A Resilient System Design to Boot a RISC-V MPSoC
brain tumor	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
breadth-first search	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
C
cancer	Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
Cancer diagnosis	Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing
Cervical cancer	Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia
Cervical Intraepithelial Neoplasia (CIN)	Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia
CFI	A CFI Verification System based on the RISC-V Instruction Trace Encoder
Chip Multiprocessors	Coherency Traffic Reduction in Manycore Systems
cipher	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment
Circuit Synthesis	PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML
Clustering	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
CMPs	Coherency Traffic Reduction in Manycore Systems
CNN accelerator	Hardware-Software Codesign of a CNN Accelerator
code generation	Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
code-based cryptography	FPGA implementation of BIKE for quantum-resistant TLS
Cognitive system	Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project
Coherency	Coherency Traffic Reduction in Manycore Systems
collective communication	RED-SEA: Network Solution for Exascale Architectures
Communication	Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach
Compression	CaW-NAS: Compression Aware Neural Architecture Search
computation efficiency	ARTS: An adaptive regularization training schedule for activation sparsity exploration
Computer Aided Engineering	Abeto framework: a Solution for Heterogeneous IP Management
Computer Architecture	Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the Best?
computer vision	PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
computing array	Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
Condition Monitoring	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
congestion mechanism	RED-SEA: Network Solution for Exascale Architectures
continuous system engineering	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
Contrast agents	In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging
Control-flow integrity	Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems
Controlling	Sense and Control of Oscillating MEMS Mirrors
Convolutional Neural Network	POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications
Convolutional neural networks (CNNs)	CPU-GPU Layer-Switched Low Latency CNN Inference An FPGA based Tiled Systolic Array Generator to Accelerate CNNs
convolutional-neural-networks	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
Coordinate rotation digital computer (CORDIC)	RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
Coordinate-based Scoring	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
Countermeasures	SecDec : Secure Decode Stage thanks to masking of instructions with the generated signals
CPPS development	How are Industry 4.0 Reference Architectures Used in CPPS Development?
CPU-GPU tandem	Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem
cryptography	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
CV	A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks
Cyber Physical Systems (CPS)	Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm
cybersecurity	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
D
Data representation in RRAM crossbars	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Data-Intensive Application	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
Database Management	Abeto framework: a Solution for Heterogeneous IP Management
datacenter	RED-SEA: Network Solution for Exascale Architectures
Decision Tree	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
decomposition	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
deep learning	Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention ARTS: An adaptive regularization training schedule for activation sparsity exploration Attention-based Skin Cancer Classification Through Hyperspectral Imaging CaW-NAS: Compression Aware Neural Architecture Search CELR: Cloud Enhanced Local Reconstruction from Low-dose Sparse Scanning Electron Microscopy Images TextBack: Watermarking Text Classifiers using Backdooring Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
Deep Neural Network	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
Deep neural network optimisation	Inference Time Reduction of DNNs on Embedded Devices: A Case Study
Deep Neural Networks (DNN)	Co-Optimization of DNN and Hardware Configurations on Edge GPUs
deep-learning	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
Design for testability	Nonlinear Compression Block Codes Search Strategy
Design Space Exploration	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Directory	Coherency Traffic Reduction in Manycore Systems
Disassembly	Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
Distributed Cyber-Physical Systems	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Distributed Learning	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
Distributed Simulation	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
Distributed system sustainability	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
domain specific accelerators	Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
Drones	COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations
DSP delay lines	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
DVS	Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
Dynamic Dependability Management	Skeptical Dynamic Dependability Management for Automated Systems
dynamic partial reconfiguration	Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
Dynamic Risk Management	Skeptical Dynamic Dependability Management for Automated Systems
dynamic vision sensor	Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
E
Earliest Deadline First Scheduling	A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
Early-exit	Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks
EDF	Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
edge AI	Inference Time Reduction of DNNs on Embedded Devices: A Case Study
Edge Computing	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project CPU-GPU Layer-Switched Low Latency CNN Inference
edge detection	ESAS: Exponent Series based Approximate Square Root Design PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
edge devices	PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices
Efficient programming of RRAM crossbars	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
efficient training	ARTS: An adaptive regularization training schedule for activation sparsity exploration
Elderly Fall Detection	GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
Electronic Design Automation	Abeto framework: a Solution for Heterogeneous IP Management
EM analysis	Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
embedded deep learning	Inference Time Reduction of DNNs on Embedded Devices: A Case Study
Embedded Systems	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems Quantization: how far should we go? Verifying Liveness and Real-Time of OS-Based Embedded Software moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
Energy	Quantization: how far should we go?
energy efficiency	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
energy reduction	ARTS: An adaptive regularization training schedule for activation sparsity exploration
error metrics	Designing Approximate Arithmetic Circuits with Combined Error Constraints
ESL	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
EUREKA	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
event camera	Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
Event-Driven Programming	Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
evolutionary algorithm	Co-Optimization of DNN and Hardware Configurations on Edge GPUs
evolutionary algorithms	Designing Approximate Arithmetic Circuits with Combined Error Constraints
Exact Synthesis	SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
exergames	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
exposed datapath	Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
F
fall prevention	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
Fault Attack	Blind Data Adversarial Bit-flip Attack against Deep Neural Networks
Fault detection	SecDec : Secure Decode Stage thanks to masking of instructions with the generated signals
fault injection	Variable-Length Instruction Set: Feature or Bug?
Fault injection attack	SecDec : Secure Decode Stage thanks to masking of instructions with the generated signals
fault model	Variable-Length Instruction Set: Feature or Bug?
Fault Prediction	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
Fault Tolerance	Towards Resilient QDI Pipeline Implementations
Fault tolerant systems	Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation
Fault Tree Analysis	EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis
Federated Learning	A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
FIA	A CFI Verification System based on the RISC-V Instruction Trace Encoder
Field Programmable Gate Array (FPGA)	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
filtering	Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
Fixed Priority Scheduling	A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
Flight Safety	Optimizing UAV Location Awareness Telemetry for Low Power Wide Area Network
Formal methods	Real-Time Polling Task: Design and Analysis
Formal Methods in System Design	A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
Formal Verification	Verifying Liveness and Real-Time of OS-Based Embedded Software Polynomial Formal Verification of Approximate Adders
FPGA	FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm FPGA implementation of BIKE for quantum-resistant TLS Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection High-Level Synthesis of Geant4 Particle Transport Application for FPGA A Majority-based Approximate Adder for FPGAs Implementation of the Rainbow signature scheme on SoC FPGA Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms An FPGA based Tiled Systolic Array Generator to Accelerate CNNs Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip A Resilient System Design to Boot a RISC-V MPSoC A CFI Verification System based on the RISC-V Instruction Trace Encoder Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
FPGA SoCs	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
FPGAs	Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks
FPGAs in the Cloud	Towards Hardware Support for FPGA Resource Elasticity
Free-choice Petri net	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
G
Gait analysis	GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
Geant4	High-Level Synthesis of Geant4 Particle Transport Application for FPGA
glioblastoma	Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
GoodBrother	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
GPU	Co-Optimization of DNN and Hardware Configurations on Edge GPUs
graph	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
graph processing	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
Graph theory	Nonlinear Compression Block Codes Search Strategy
grid search	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Guessing Entropy	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
H
Hamming Weight Leakage Model	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
Hardware	A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
Hardware Acceleration	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks
Hardware Accelerator	ESAS: Exponent Series based Approximate Square Root Design ImageSpec: Efficient High-Level Synthesis of Image Processing Applications Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Device
hardware accelerators	FPGA implementation of BIKE for quantum-resistant TLS An FPGA based Tiled Systolic Array Generator to Accelerate CNNs
hardware and software redundancy	A holistic hardware-software approach for fault-aware embedded systems
Hardware description language (HDL)	RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
hardware design	Implementation of the Rainbow signature scheme on SoC FPGA
hardware security	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
hardware security protocols	Mobile Systems Secure State Management
hardware software co-design	moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
Hardware Verification	IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets
hardware-aware neural architecture search	CaW-NAS: Compression Aware Neural Architecture Search
Hardware/Software Co-Design	Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Device
HDR enhancement	PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
Health-condition	On the Validation of Multi-Level Personalised Health Condition Model
hemoglobin	Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
Heterogeneous Embedded Systems	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Heterogeneous Multiprocessor System-on-Chip	CPU-GPU Layer-Switched Low Latency CNN Inference
Heterogeneous Platforms	Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
Heterogeneous systems	SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing
Heterogeneous virtualization	Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores
Hierarchical systems	Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation
High performance	An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
High-Level Synthesis	ImageSpec: Efficient High-Level Synthesis of Image Processing Applications Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis
histology	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
HLS	High-Level Synthesis of Geant4 Particle Transport Application for FPGA
HPC	RED-SEA: Network Solution for Exascale Architectures
HUD	Sense and Control of Oscillating MEMS Mirrors
Human Activity Recognition	GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
HW/SW codesign	Hardware-Software Codesign of a CNN Accelerator
hyperparameter	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
hyperspectral	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
hyperspectral images	Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing
hyperspectral imaging	Reflectance Calibration with Normalization Correction in Hyperspectral Imaging Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Hyperspectral imaging instrumentation	Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia
I
IC trust	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
IIRA	How are Industry 4.0 Reference Architectures Used in CPPS Development?
image processing	Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia ImageSpec: Efficient High-Level Synthesis of Image Processing Applications PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
Image reconstruction	CELR: Cloud Enhanced Local Reconstruction from Low-dose Sparse Scanning Electron Microscopy Images
In vitro testbed	In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging
in-memory computing	Generation of Verified Programs for In-Memory Computing Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
Industry 4.0	How are Industry 4.0 Reference Architectures Used in CPPS Development?
Inference Latency	CPU-GPU Layer-Switched Low Latency CNN Inference
InfiniBand	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
Integer Linear Programming	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Intelligent Totems	Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project
Interconnect	RED-SEA: Network Solution for Exascale Architectures
interconnection network	Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
Internet of Things	Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project
IP Cores	Abeto framework: a Solution for Heterogeneous IP Management
IP obfuscation	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
IP protection	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
ISE	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment
ITEA	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
J
jitter	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
junction trees	Partial Evaluation in Junction Trees
K
k-red	Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber
L
large model inference	PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices
lattice-based cryptography	Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber
Leakage Assessment	Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box
LiDAR	Sense and Control of Oscillating MEMS Mirrors
LiM-HDL	Generation of Verified Programs for In-Memory Computing
linear regression model	Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
LLVM	Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
load cell	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
Logic implementation with RRAM crossbars	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Logistic Regression	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
Look-up-Table	POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications
LoRaWAN	Optimizing UAV Location Awareness Telemetry for Low Power Wide Area Network
low error	A Majority-based Approximate Adder for FPGAs
Low Power	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
low-cost	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
Low-dose Sparse Scanning	CELR: Cloud Enhanced Local Reconstruction from Low-dose Sparse Scanning Electron Microscopy Images
Low-Latency Ethernet	RED-SEA: Network Solution for Exascale Architectures
low-power design	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
LSTM	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
LWE/LWR-based KEM	Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
M
machine learning	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical Systems
Majorization	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
Manycores	Coherency Traffic Reduction in Manycore Systems
Masking	SecDec : Secure Decode Stage thanks to masking of instructions with the generated signals Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box
massively parallel computers	Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
Matrix-Vector-Multiplication (MVM)	MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories
MEDA biochip	MEDA Biochip based Single-Target Fluidic Mixture Preparation with Minimum Wastage
medical hyperspectral imaging	Attention-based Skin Cancer Classification Through Hyperspectral Imaging
Memristor	MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories
memristor crossbar	Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
MEMS mirror	Sense and Control of Oscillating MEMS Mirrors
message passing	Partial Evaluation in Junction Trees
Methodology development	Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology
microfluidic biochip	MEDA Biochip based Single-Target Fluidic Mixture Preparation with Minimum Wastage
microscopy	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
Minimum clique cover problem	Nonlinear Compression Block Codes Search Strategy
Mixed Criticality Systems	Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
Mixed-Criticality	A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
Mixed-criticality Systems	Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms
mixing	MEDA Biochip based Single-Target Fluidic Mixture Preparation with Minimum Wastage
ML frameworks	Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem
mobile devices	Mobile Systems Secure State Management
mobile platform	CaW-NAS: Compression Aware Neural Architecture Search
mobilenet	Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention
Model Inference	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Model-based analysis	Real-Time Polling Task: Design and Analysis
modeling	DNAsim: Evaluation Framework for Digital Neuromorphic Architectures Real-Time Polling Task: Design and Analysis
Monitoring	Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms
Monte Carlo Simulation	EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis
MRI	In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging
Multi-Processor System-on-Chip (MPSoC)	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform
Multi-Value CiM	MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories
Multicore processing	Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores
multilevel modelling	On the Validation of Multi-Level Personalised Health Condition Model
Multiplier	An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
multispectral imaging	Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
multivariate quadratic	Implementation of the Rainbow signature scheme on SoC FPGA
N
Network-on-Chip	Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
Neural Network	Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Device Blind Data Adversarial Bit-flip Attack against Deep Neural Networks
Neural network accelerators	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Neural Networks	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems TextBack: Watermarking Text Classifiers using Backdooring
Neural processing unit	Hardware-Software Codesign of a CNN Accelerator
neuromoprhic	DNAsim: Evaluation Framework for Digital Neuromorphic Architectures
noise models	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
nonlinear mixing models	Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing
NTV	SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing
Number Systems	Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the Best?
number theoretic transform	Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber
O
Object Detection	A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
On-Chip Inference	CPU-GPU Layer-Switched Low Latency CNN Inference
open source hardware	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
open-source
operating system	moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
Operational Design Domain	Skeptical Dynamic Dependability Management for Automated Systems
optical filters	Reflectance Calibration with Normalization Correction in Hyperspectral Imaging
optical imaging	Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
Optimization	ImageSpec: Efficient High-Level Synthesis of Image Processing Applications A resolution method in case of air congestion: rerouting and/or ground holding approach
P
PAIG synthesis	Technology Mapping for PAIG Optimised Polymorphic Circuits
PAIG technology mapping	Technology Mapping for PAIG Optimised Polymorphic Circuits
parallel execution	PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices
partial evaluation	Partial Evaluation in Junction Trees
Partial Reconfiguration	A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
Pathology	Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
PDES	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
perception architecture design	Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical Systems
Perception System	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
Performance Modeling	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
personalized healthcare	On the Validation of Multi-Level Personalised Health Condition Model
Petri net	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
phase noise	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
PHM	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
Pipelines	Towards Resilient QDI Pipeline Implementations
platoon	A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks
PLiM	Generation of Verified Programs for In-Memory Computing
Pointer analysis	Coherency Traffic Reduction in Manycore Systems
polar codes	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
polymorphic electronics	Technology Mapping for PAIG Optimised Polymorphic Circuits
polymorphic gates	Technology Mapping for PAIG Optimised Polymorphic Circuits
Posit Arithmetic	PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML
Position Awareness	Optimizing UAV Location Awareness Telemetry for Low Power Wide Area Network
posits	PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
Post-Quantum	Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices
post-quantum cryptography	FPGA implementation of BIKE for quantum-resistant TLS Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber Implementation of the Rainbow signature scheme on SoC FPGA Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis
power consumption	Co-Optimization of DNN and Hardware Configurations on Edge GPUs
Power efficient	An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
Privacy preserving smart metering streaming	Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm
privacy-aware applications	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
probabilistic graphical models	Partial Evaluation in Junction Trees
Process in Memory	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
Processing-in-Memory	POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications
Processor	SecDec : Secure Decode Stage thanks to masking of instructions with the generated signals
processor architecture	moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
profiling	Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem
pseudo-Boolean optimization	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
Pseudo-exhaustive testing	Nonlinear Compression Block Codes Search Strategy
public-key cryptography	Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
Q
QC-MDPC codes	FPGA implementation of BIKE for quantum-resistant TLS
QDI	Towards Resilient QDI Pipeline Implementations
QoS	RED-SEA: Network Solution for Exascale Architectures
Quantization	Quantization: how far should we go?
Quantum computing	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
R
Radar	GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
RAMI4.0	How are Industry 4.0 Reference Architectures Used in CPPS Development?
random forest	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
random search	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Real-Time	A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
Real-time Analysis	Real-Time Polling Task: Design and Analysis
Real-Time Operating Systems	Verifying Liveness and Real-Time of OS-Based Embedded Software
Real-time Systems	Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
Real-time Tasks	A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
Reconfigurable Crossbar	Towards Hardware Support for FPGA Resource Elasticity
Reconfigurable Hardware	Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
Reduced instruction set architecture	RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
Reduced Instruction Set Computing	Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the Best?
Reference architectures	How are Industry 4.0 Reference Architectures Used in CPPS Development?
reflectance calibration	Reflectance Calibration with Normalization Correction in Hyperspectral Imaging
Reliability	EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation
Reliability engineering	Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation
Remaining Useful Life	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
ReRAM	Generation of Verified Programs for In-Memory Computing
Research project	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
Resource Elasticity	Towards Hardware Support for FPGA Resource Elasticity
Return-oriented programming	Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems
reverse engineering	Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
Reverse-Engineering	Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
ring oscillator	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
RISC-V	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform Evaluating Cryptographic Extensions On A RISC-V Simulation Environment moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems A Resilient System Design to Boot a RISC-V MPSoC A CFI Verification System based on the RISC-V Instruction Trace Encoder Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
RISCV	Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
Robot Operating System (ROS)	Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
Round Robin Scheduling	A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
routing ground holding	A resolution method in case of air congestion: rerouting and/or ground holding approach
RRAM	Generation of Verified Programs for In-Memory Computing Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
RRAM crossbars	RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Runtime Monitoring	Skeptical Dynamic Dependability Management for Automated Systems
S
Saber KEM	Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
Safety-Critical Systems	Skeptical Dynamic Dependability Management for Automated Systems Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
sample preparation	MEDA Biochip based Single-Target Fluidic Mixture Preparation with Minimum Wastage
SAT	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
scalability	Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
Scanning Electron Microscopy	CELR: Cloud Enhanced Local Reconstruction from Low-dose Sparse Scanning Electron Microscopy Images
Schedulability	Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
Scheduler Synthesis	A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
Scheduling	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Schur Concavity	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
Secure communication	Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices
Security	Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks Blind Data Adversarial Bit-flip Attack against Deep Neural Networks
security requirements	Mobile Systems Secure State Management
Sensing	Sense and Control of Oscillating MEMS Mirrors
Sentient spaces	Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project
sequential based-model optimization	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Side channel	Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box
Side-channel	Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
Side-Channel Analysis	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
side-channel attack	Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
signal processing systems	Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
simulation	A resolution method in case of air congestion: rerouting and/or ground holding approach Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
simulator	Evaluating Cryptographic Extensions On A RISC-V Simulation Environment DNAsim: Evaluation Framework for Digital Neuromorphic Architectures
skin cancer	Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention Attention-based Skin Cancer Classification Through Hyperspectral Imaging
SLIC	FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation
Small volume	In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging
smart floor	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
Smart grid privacy	Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm
sneak path	Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
SNN	DNAsim: Evaluation Framework for Digital Neuromorphic Architectures
SoC	A Resilient System Design to Boot a RISC-V MPSoC
software product lines	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
software quality	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
software variants	SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
Spatial Isolation	Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
spiking	DNAsim: Evaluation Framework for Digital Neuromorphic Architectures
SRAM	SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
STT-MRAM	MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories
Substitution Box	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
Success Rate	Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
super-resolution	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
Superpixel	FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation
support vector machine	Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Support Vector Regression	Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
surrogate model	CaW-NAS: Compression Aware Neural Architecture Search
synthesis	Spectral Super-Resolution for Hyperspectral Histological Image Synthesis with Deep Learning
System architecture	Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology
system composability	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
system on chip	Implementation of the Rainbow signature scheme on SoC FPGA
System-on-Chip	Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
SystemC TLM	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
systems security	Mobile Systems Secure State Management
Systolic array	An FPGA based Tiled Systolic Array Generator to Accelerate CNNs
systolic arrays	SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing
T
Task Allocation	Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
Task Scheduling	AxE: An Approximate–Exact Multi-Processor System-on-Chip Platform
Telemetry	Optimizing UAV Location Awareness Telemetry for Low Power Wide Area Network
TensorFlow eager execution	Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem
Ternary Reversible Circuits	SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
Test vector compression technique	Nonlinear Compression Block Codes Search Strategy
theory of regions	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
tile artifact	A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention
time-predictable computer architecture
Time-to-digital converter (TDC)	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
Timing predictability	Real-Time Polling Task: Design and Analysis
TLS	Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices
Trace Encoder	A CFI Verification System based on the RISC-V Instruction Trace Encoder
Traffic Management	COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations
Traffic Sign Recognition	POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications
Transition system	Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
True random number generator	On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
TTA	Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
U
UAV	Optimizing UAV Location Awareness Telemetry for Low Power Wide Area Network
unmixing	Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
Uppaal	Verifying Liveness and Real-Time of OS-Based Embedded Software
Urban Air Mobility	COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations
V
validation	On the Validation of Multi-Level Personalised Health Condition Model Real-Time Polling Task: Design and Analysis
variable-length instruction set	Variable-Length Instruction Set: Feature or Bug?
vector instructions	Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
verification	On the Validation of Multi-Level Personalised Health Condition Model
video data	Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
vision processor	PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
Vision Transformers	Attention-based Skin Cancer Classification Through Hyperspectral Imaging
Vitis AI	Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
W
Watermarking	TextBack: Watermarking Text Classifiers using Backdooring
Wave Union Launcher	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
WCHB	Towards Resilient QDI Pipeline Implementations
Workload Dynamism	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Workload Modeling	Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Worst-case Analysis	Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
X
Xtensa	Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems
Y
Yolo	A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
Z
zedboard	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
Zynq UltraScale+ MPSoC	Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm

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