Talk Keyword Index

TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

Shortcuts: 2 3 6 A B C D E F G H I L M N O P Q R S T U V W X Z

2
2D materials	Unleashing the Potential of 2D Material Devices in Nonlinear RF Circuits
3
32.768kHz oscillator	A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator
3DES	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
6
6G	FPGA-based Acceleration of AI Structures for RIS Applications
A
accelerator	Accelerators in Embedded Systems for Machine Learning: A RISCV View FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms
Acquisition System	SoC Architecture for Acquisition and Processing of the EMG Signal
Active baluns	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA
ADC	Time-encoded audio MEMS sensors optimized for edge computing SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
ADCs	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
AES cipher	A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
Affective Computing	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
AI	UML-Based Design Flow for Systems with Neural Networks FPGA-based Acceleration of AI Structures for RIS Applications Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
AI accelerators	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
aIGZO technologies	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
AIoT	SpeedEdge – Acceleration microarchitectures for Edge applications
Amplifiers	Super Class AB Amplifiers: A Unifying Approach
Analog computing	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
Analog integrated circuits	Super Class AB Amplifiers: A Unifying Approach
Analog-to-Information	Towards highly efficient audio processing: New Analog-to-Digital and Analog-to-Information architectures for Edge devices
Analog/mixed-signal circuits	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
APIO	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
Architectures	Making Digital N-Path Mixers
Arduino	Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense
Artificial Neural Networks (ANN)	Implementing a CNN in FPGA Programmable Logic for NILM Applications
ASIC	An ultra-low power custom IoT node for gas sensing applications
Associative memory	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
Asymmetric Multi-Processing	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
asynchronous SAR	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
automatic generation	UML-Based Design Flow for Systems with Neural Networks
Automotive	Ciber-physical System Arquitecture for AUTOSAR Automotive Framework based on 5G communications
AUTOSAR	Ciber-physical System Arquitecture for AUTOSAR Automotive Framework based on 5G communications
AXI	HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
B
baremetal	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
battery control	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework
battery diagnosis	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework
battery use	A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator
Behavioral Modeling	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
behavioral models	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
Benchmarking	RISC-V for Genome Data Analysis: Opportunities and Challenges
Biosignals monitoring	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
BLE mote	QChain Node: an IoT based Mote for Remote Medicine Quality Monitoring
Brain-Computer Interfaces	Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense
C
Cache coherent protocols	PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration
Calibration	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Cardiovascular diseases	Configurable electrical stimulation system for cardiac tissue samples
cartography	Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks
cascode compensation	Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation Performance
Character recognition	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
chip manufacturing	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
class AB amplifiers	Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation Performance
Class AB circuits	Super Class AB Amplifiers: A Unifying Approach
client-server	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
clock gating cells	SET and SEU Hardened Clock Gating Cell
Clock Managers	Maximum Operating Frequency Self-Tuning System on FPGAs Using Dynamic Reconfiguration
CMOS	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
CMOS analog circuits	GBW Optimization in Two-Stage OTAs Operating in Weak Inversion
CMOS integrated circuit	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
CMOS integrated circuits	Super Class AB Amplifiers: A Unifying Approach
CMOS models	CMOS Transistor Array for Cryogenic Temperature Characterization of MOS Components
CNN	UML-Based Design Flow for Systems with Neural Networks
communication semantics	Automatic code generation from UML for data memory optimization in microcontrollers
complementary resistive switch	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
Computer architecture exploration	PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration
Contactless current measurement	High Resolution Current Measurement Using TMR Sensors
contrast test	Real-time iris image quality evaluation implemented in Ultrascale MPSoC
Convolutional Neural Networks	Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense Approximate arithmetic aware training for stochastic computing neural networks
correlator bank	Definition of a SoC Architecture for a High-Rate Correlator Bank
Corrosion monitoring	SMART CORROSION MONITORING BASED ON NON-DESTRUCTIVE TESTINGS (NDTs)
critical charge	A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
cross-compiled simulation	Improvement of the estimation of execution cycles of Application SW for Cross-Compiled Simulation of RISC-V Platforms using AI
crs	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
Cryo-CMOS	CMOS Transistor Array for Cryogenic Temperature Characterization of MOS Components
Cryogenic measurement	CMOS Transistor Array for Cryogenic Temperature Characterization of MOS Components
Cuk Converter	Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic System
Current probe	High Resolution Current Measurement Using TMR Sensors
current source	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
Cyber-physical system	Ciber-physical System Arquitecture for AUTOSAR Automotive Framework based on 5G communications
Cyber-physical system (CPS)	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework
D
DAS	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
Data acquisition systems	Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis
design methodologies	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
Design Space Exploration	UML-Based Design Flow for Systems with Neural Networks SpeedEdge – Acceleration microarchitectures for Edge applications
device characterization	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
Differential Power Analysis attack	A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
Digital	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Digital Filter	Making Digital N-Path Mixers
Digital Lock-In Amplifier	Design Space Analysis for a Digital Lock-In Amplifier for Infrarred Gas Sensor Signal Acquisition
Digital N-path Mixer	Making Digital N-Path Mixers
Digital Signal Processing	Any-Radix Efficient Parallel Implementation of the Fast Fourier Transform on FPGAs Design Space Analysis for a Digital Lock-In Amplifier for Infrarred Gas Sensor Signal Acquisition
Digitalization	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
DNN	SpeedEdge – Acceleration microarchitectures for Edge applications
DPS	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
DPU	Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
DPVAR	Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations
Dynamic time warping	High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS
dynamic vision sensor	Study of foveation mechanisms in Dynamic Vision Sensors
E
ECU 5G	Ciber-physical System Arquitecture for AUTOSAR Automotive Framework based on 5G communications
Edge computing	Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense Approximate arithmetic aware training for stochastic computing neural networks Inertial-Instrument for Monitoring Offshore-Cage Mooring-Line Dynamics Oceanographic Profiler for Long-Term Measurements of Energy and Tidal Currents SpeedEdge – Acceleration microarchitectures for Edge applications
EEGNet	Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 Sense
Efficiency	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
electric vehicle	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework
Electrical stimulation	Configurable electrical stimulation system for cardiac tissue samples
Electromagnetic Fault Injection	Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks
Electronic design automation	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
electronics teaching	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
embedded	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
embedded implementations on-the-edge	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
embedded intelligence	Oceanographic Profiler for Long-Term Measurements of Energy and Tidal Currents
EMG Signal	SoC Architecture for Acquisition and Processing of the EMG Signal
energy efficiency	Accelerators in Embedded Systems for Machine Learning: A RISCV View
Ethernet Emulation	Ethernet Emulation over PCIe for RISC-V Software Development Vehicles
event coding	Study of foveation mechanisms in Dynamic Vision Sensors
Ex vivo research	Configurable electrical stimulation system for cardiac tissue samples
Exoskeleton	SoC Architecture for Acquisition and Processing of the EMG Signal
Eye detection	Real-time iris image quality evaluation implemented in Ultrascale MPSoC Real-time embedded eye detection and analysis framework
F
Fast Fourier transform (FFT)	A 5.2-GS/s 8-Parallel 1024-Point MDC FFT An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond
fast-transient response	Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation Performance
Fault injection	Evaluating the soft error sensitivity of LU decomposition on low-power and high-performance GPUs Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks
FFT	Any-Radix Efficient Parallel Implementation of the Fast Fourier Transform on FPGAs
field-effect	On the influence of technological parameters on the expected performance of GFET-based mixers.
Field-Programmable Gate Array (FPGA)	Implementing a CNN in FPGA Programmable Logic for NILM Applications
Field-Programmable Gate Arrays	Comparative Analysis of Neural Network Implementations for NILM Applications
Filter	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
FLASH FPGA	Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking
flexible microelectronics	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
Fourier Transform	Any-Radix Efficient Parallel Implementation of the Fast Fourier Transform on FPGAs
foveation	Study of foveation mechanisms in Dynamic Vision Sensors
FPGA	Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations Any-Radix Efficient Parallel Implementation of the Fast Fourier Transform on FPGAs UML-Based Design Flow for Systems with Neural Networks Ethernet Emulation over PCIe for RISC-V Software Development Vehicles HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip Design Space Analysis for a Digital Lock-In Amplifier for Infrarred Gas Sensor Signal Acquisition Real-time iris image quality evaluation implemented in Ultrascale MPSoC PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration High-Rate Acquisition System for an Infrared LPS Maximum Operating Frequency Self-Tuning System on FPGAs Using Dynamic Reconfiguration Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Real-time embedded eye detection and analysis framework SpeedEdge – Acceleration microarchitectures for Edge applications FPGA-based Acceleration of AI Structures for RIS Applications Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks Definition of a SoC Architecture for a High-Rate Correlator Bank Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
FPGA acceleration	High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS
FPGA implementation	FPGA Implementation of Sherman-Morrison Formula Using High-Level Synthesis and Graphical Blocks Programming
Frequency Response	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
fringed patterns	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
G
gas sensor	An ultra-low power custom IoT node for gas sensing applications
generator	An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond
Genesys-2	HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
Genome Analysis	RISC-V for Genome Data Analysis: Opportunities and Challenges
gm/ID	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA
GPU	Evaluating the soft error sensitivity of LU decomposition on low-power and high-performance GPUs
Graphene	Devices and circuits for HF applications based on 2D materials On the influence of technological parameters on the expected performance of GFET-based mixers.
graphene transistor	Design of GFET-based active modulators leveraging device performance reproducibility conditions
graphene transistors	Devices and circuits for HF applications based on 2D materials
Graphical blocks programming	FPGA Implementation of Sherman-Morrison Formula Using High-Level Synthesis and Graphical Blocks Programming
H
Haar-like features	Real-time iris image quality evaluation implemented in Ultrascale MPSoC
Hardware acceleration	Run-Time ML-Based Modeling and Management of Reconfigurable Multi-Accelerator Systems with Virtualization Support SpeedEdge – Acceleration microarchitectures for Edge applications
Hardware implementation	Any-Radix Efficient Parallel Implementation of the Fast Fourier Transform on FPGAs
hardware security	Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks
HDL	FPGA-based Acceleration of AI Structures for RIS Applications
Heterogeneous systems	PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration
high frequency	On the influence of technological parameters on the expected performance of GFET-based mixers.
high frequency electronics	Devices and circuits for HF applications based on 2D materials
high-frequency	Design of GFET-based active modulators leveraging device performance reproducibility conditions
High-level synthesis	FPGA Implementation of Sherman-Morrison Formula Using High-Level Synthesis and Graphical Blocks Programming
high-speed communications	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
HLS	FPGA-based Acceleration of AI Structures for RIS Applications SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
HLS implementation	High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS
Hopfield neural networks	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
HPC	RISC-V for Genome Data Analysis: Opportunities and Challenges
HSI	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
hypervisor	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
I
iCE40	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
Indoor optical positioning system	Definition of a SoC Architecture for a High-Rate Correlator Bank
infrared	High-Rate Acquisition System for an Infrared LPS
integrated circuit design	Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
Integrated circuits	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
Integrated Converter	Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic System
Inter-modulation	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
interfacing	Time-domain Architectures for Interfacing Phase Change Memory
Interleaving	High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS
Internet of Things (IoT)	An ultra-low power custom IoT node for gas sensing applications
Internet of Thinks nodes	QChain Node: an IoT based Mote for Remote Medicine Quality Monitoring
IoT	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework
L
latency	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
LFSR seed	Approximate arithmetic aware training for stochastic computing neural networks
LIF	FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
light emitting diode (LED)	An ultra-low power custom IoT node for gas sensing applications
Linearity	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Linearization	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Linux	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
Low latency	FPGA Implementation of Sherman-Morrison Formula Using High-Level Synthesis and Graphical Blocks Programming
low power	An ultra-low power custom IoT node for gas sensing applications A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator SET and SEU Hardened Clock Gating Cell
Low power design	GBW Optimization in Two-Stage OTAs Operating in Weak Inversion
Low-dropout regulator	Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation Performance
LU decomposition	Evaluating the soft error sensitivity of LU decomposition on low-power and high-performance GPUs
LUT	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
M
Machine Learning	Machine learning infrastructure for managing a electric vehicle fleet using a cyber-physical system framework Run-Time ML-Based Modeling and Management of Reconfigurable Multi-Accelerator Systems with Virtualization Support Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing Systems
Machine learning algorithms	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
machine-learning	Improvement of the estimation of execution cycles of Application SW for Cross-Compiled Simulation of RISC-V Platforms using AI
Many-core	PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration
matched filtering	Definition of a SoC Architecture for a High-Rate Correlator Bank
Maximum operating frequency	Maximum Operating Frequency Self-Tuning System on FPGAs Using Dynamic Reconfiguration
medicine quality	QChain Node: an IoT based Mote for Remote Medicine Quality Monitoring
memory optimization	Automatic code generation from UML for data memory optimization in microcontrollers
memristor	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series Time-domain Architectures for Interfacing Phase Change Memory
MEMS sensor	Time-encoded audio MEMS sensors optimized for edge computing
metastability	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
Meteorological sensors	Design Space Analysis for a Digital Lock-In Amplifier for Infrarred Gas Sensor Signal Acquisition
Microarchitectures	SpeedEdge – Acceleration microarchitectures for Edge applications
microcontrollers	Automatic code generation from UML for data memory optimization in microcontrollers
Microwave	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA
Miller compensation	GBW Optimization in Two-Stage OTAs Operating in Weak Inversion
Mixed-signal neuromorphic circuits	Towards highly efficient audio processing: New Analog-to-Digital and Analog-to-Information architectures for Edge devices
mixers	Unleashing the Potential of 2D Material Devices in Nonlinear RF Circuits
MMTES	Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations
modulated light	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
modulation	Design of GFET-based active modulators leveraging device performance reproducibility conditions
mooring-line dynamics	Inertial-Instrument for Monitoring Offshore-Cage Mooring-Line Dynamics
MPPT	Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations
MTD	A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
Multi-electrode array	Configurable electrical stimulation system for cardiac tissue samples
multi-path delay commutator (MDC)	A 5.2-GS/s 8-Parallel 1024-Point MDC FFT
Multi-Processor System on Chip	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
Multi-standard	Making Digital N-Path Mixers
N
Nano-oscillators	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
Neural Networks	Comparative Analysis of Neural Network Implementations for NILM Applications Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
Neuromorphic	FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
Neuromorphic computing	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
Neuromorphic hardware	Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators
NGVA	Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
NN	FPGA-based Acceleration of AI Structures for RIS Applications Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
NoC	PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration
non-destructive testing	SMART CORROSION MONITORING BASED ON NON-DESTRUCTIVE TESTINGS (NDTs)
Non-Intrusive Load Monitoring	Comparative Analysis of Neural Network Implementations for NILM Applications
Non-Intrusive Load Monitoring (NILM)	Implementing a CNN in FPGA Programmable Logic for NILM Applications
non-power-of-two (NP2) size	An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond
NTRU	A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
O
oceanographic instrument	Inertial-Instrument for Monitoring Offshore-Cage Mooring-Line Dynamics Oceanographic Profiler for Long-Term Measurements of Energy and Tidal Currents
offshore	SMART CORROSION MONITORING BASED ON NON-DESTRUCTIVE TESTINGS (NDTs)
On-Board	Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking
On-chip training	Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing Systems
open-source	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
OpenAMP	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
optical positioning system	High-Rate Acquisition System for an Infrared LPS
Oscillators	A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
Oscillatory neural networks	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
Oscillatory neural networks (ONNs)	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
P
Pattern recognition	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
PCM	Time-domain Architectures for Interfacing Phase Change Memory
Phase transition materials	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
Phase-change material	Novel Iterative Hebbian Learning Rule for Oscillatory Associative Memory
photodiode	An ultra-low power custom IoT node for gas sensing applications
Photovoltaic System	Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic System
Pierce oscillator	A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator
pipelined architecture	A 5.2-GS/s 8-Parallel 1024-Point MDC FFT
Post-Quantum Cryptography	A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
power consumption	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
Power Electronics	Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic System
Programmability	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
projection	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
Pruning	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
PSK	Design of GFET-based active modulators leveraging device performance reproducibility conditions
Pulse Shaping	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
PyNN	FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
PYNQ	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
Python	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
Q
Quality Chain	QChain Node: an IoT based Mote for Remote Medicine Quality Monitoring
Quantization (signal)	Approximate arithmetic aware training for stochastic computing neural networks
quartz crystal	A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator
R
Radiation	Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis
radiation hardening	A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
radiation hardness	SET and SEU Hardened Clock Gating Cell
radiofrequency	Unleashing the Potential of 2D Material Devices in Nonlinear RF Circuits
RAM	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Readout system	Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis
real-time	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
realtime image processing	Real-time embedded eye detection and analysis framework
Reconfigurable Computing	Run-Time ML-Based Modeling and Management of Reconfigurable Multi-Accelerator Systems with Virtualization Support
rectifiers	Unleashing the Potential of 2D Material Devices in Nonlinear RF Circuits
Redundancy Elimination	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
reram	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
Reservoir Computing	Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing Systems
resistive memory	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
resistive switch	Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series
RF	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA
RF switches	Devices and circuits for HF applications based on 2D materials
Ring Oscillator	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters
Ring Oscillators	Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition
RIS	FPGA-based Acceleration of AI Structures for RIS Applications
RISC-V	Accelerators in Embedded Systems for Machine Learning: A RISCV View Ethernet Emulation over PCIe for RISC-V Software Development Vehicles HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology PEAK: An Open-Source FPGA platform for Many-Core Architecture Exploration RISC-V for Genome Data Analysis: Opportunities and Challenges Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking RTL Modeling of the RV32I Architecture with SystemC Improvement of the estimation of execution cycles of Application SW for Cross-Compiled Simulation of RISC-V Platforms using AI FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms SpeedEdge – Acceleration microarchitectures for Edge applications
RISC-V microprocessor	Design Space Analysis for a Digital Lock-In Amplifier for Infrarred Gas Sensor Signal Acquisition
RSA	HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip
RTL	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
RTL design	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
RV32I	RTL Modeling of the RV32I Architecture with SystemC
S
Security comparison	A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
Sensitivity	Evaluating the soft error sensitivity of LU decomposition on low-power and high-performance GPUs
sensors	SMART CORROSION MONITORING BASED ON NON-DESTRUCTIVE TESTINGS (NDTs)
SFDI	Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications
Sherman-Morrison	FPGA Implementation of Sherman-Morrison Formula Using High-Level Synthesis and Graphical Blocks Programming
Sigma Delta	Time-encoded audio MEMS sensors optimized for edge computing
simulation	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
single event transient	A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
Single Event Transient (SET)	SET and SEU Hardened Clock Gating Cell
single event upset	A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
Single Event Upset (SEU)	SET and SEU Hardened Clock Gating Cell
Single Power Analysis	A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem
Single-ended to differential LNA	Output Phase and Gain Error Reduction Design-Oriented Single-Ended to Differential LNA
single-path delay feedback (SDF)	An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond
SNN	FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
SoC	HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking Exploration of Fast Sinewave Pattern Generation and Projection in a SoC-based System for Spatial Frequency Domain Imaging Applications Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
SoC FPGA	Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations
soft error	SET and SEU Hardened Clock Gating Cell
Soft errors	Evaluating the soft error sensitivity of LU decomposition on low-power and high-performance GPUs A Compact Double-Exponential Circuit for Single Event Transient (SET) Emulation
Software Defined Radio	Making Digital N-Path Mixers
Spacecraft	Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking
SpaceWire	Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking
Spectroscopy	Digital Spectroscopy Channel Integrated into a SoC for Testing and Analysis
spiking	FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks
Spiking Neural Networks	Towards highly efficient audio processing: New Analog-to-Digital and Analog-to-Information architectures for Edge devices
SRAM	Experimental cartography generation methodology for Electromagnetic Fault Injection Attacks
SRAM FPGA	Design and Evaluation of a RISC-V based SoC for Satellite on-board Networking
statistical characterization	CMOS Transistor Array for Cryogenic Temperature Characterization of MOS Components
Stimulation artifact	Configurable electrical stimulation system for cardiac tissue samples
Stochastic computing	Approximate arithmetic aware training for stochastic computing neural networks Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing Systems
Subharmonic injection locking	Experimental Demonstration of Associative Memory in Coupled Differential Oscillator Networks
subharmonic mixer	On the influence of technological parameters on the expected performance of GFET-based mixers.
System Modeling	Run-Time ML-Based Modeling and Management of Reconfigurable Multi-Accelerator Systems with Virtualization Support
system on chip	Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
System-on-Chip	SoC Architecture for Acquisition and Processing of the EMG Signal
System-on-Chip (SoC)	Implementing a CNN in FPGA Programmable Logic for NILM Applications
SystemC	RTL Modeling of the RV32I Architecture with SystemC
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tidal-current-meter	Inertial-Instrument for Monitoring Offshore-Cage Mooring-Line Dynamics Oceanographic Profiler for Long-Term Measurements of Energy and Tidal Currents
time domain	Time-domain Architectures for Interfacing Phase Change Memory
time interleaving	ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers
Timing analysis	Maximum Operating Frequency Self-Tuning System on FPGAs Using Dynamic Reconfiguration
transistor	On the influence of technological parameters on the expected performance of GFET-based mixers.
traps	Design of GFET-based active modulators leveraging device performance reproducibility conditions
TSN	Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence Applications
Tunability	Making Digital N-Path Mixers
Tunnel MagnetoResistance	High Resolution Current Measurement Using TMR Sensors
two-stage amplifier	GBW Optimization in Two-Stage OTAs Operating in Weak Inversion A Two-Stage Amplifier in a Low Power 32.768kHz Quartz Crystal Oscillator
U
Ultrascale+ MP SoC	Real-time iris image quality evaluation implemented in Ultrascale MPSoC Real-time embedded eye detection and analysis framework
UML	UML-Based Design Flow for Systems with Neural Networks Automatic code generation from UML for data memory optimization in microcontrollers
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VCO	Maximally Digital VCO-based ADCs with Programmable Pulse Shaping Filters Time-encoded audio MEMS sensors optimized for edge computing
VCO-ADCs	Towards highly efficient audio processing: New Analog-to-Digital and Analog-to-Information architectures for Edge devices
Verilog	Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools
VHDL	An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond
virtualization	Run-Time ML-Based Modeling and Management of Reconfigurable Multi-Accelerator Systems with Virtualization Support Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
Vivado	Exploring Open-Source and Proprietary Design Tools to Implement a Symmetric Cipher on FPGAs
Volterra Model	Complexity Reduction of Baseband Volterra Modeling for Low Memory Cases
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weak inversion operation	GBW Optimization in Two-Stage OTAs Operating in Weak Inversion
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Xen	Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments
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ZedBoard	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics
Zynq	SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics