ABSTRACT. This document introduces a wide-spreading project that allows engineering students to design, simulate, verify and manufacture a custom RTL design using HDL languages alongside a RISC-V core. To solve the deficiencies regarding functional core verification that this project features, this paper proposes the adoption of UVM and Python-based verification tools.

ABSTRACT. Many-core architectures, especially those with heterogeneous components, are gaining momentum due to the benefits of having an Open Source ISA (RISC-V). In this paper we introduce PEAK, an FPGA platform that can be effectively used for many-core exploration when using RISCV processors. The platform defines a coherence protocol and provides an efficient interconnect. Therefore, RISC-V processors can be embedded as placeholders, resulting on a ready manycore system. We provide also tools to control, manange, and debug the system.

ABSTRACT. This paper describes the [blinded] System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology. The SoC includes the processor as well as, among other components, a Phase Locked Loop (PLL) operating up to 2 GHz, interfaces to HyperRAM and a Serdes up to 8 Gbps. The processor has demonstrated experimental correct operation at 800 MHz.

ABSTRACT. This work presents a low power 32.768kHz quartz crystal oscillator in 18nm CMOS technology. Various driving modes are available to address all quartz crystals on the market. Each mode is designed to reach the best power consumption according to the crystal requirements. Experimental results show a power consumption of 90nA under 1.8V supply (i.e. 162nW) in the ultra-low power mode working with a specific quartz crystal, over a reduced temperature and power supply range.

ABSTRACT. This paper presents a single-ended-to-differential low-noise amplifier (LNA) topology that jointly minimizes both its outputs’ magnitude difference and the departure from their ideal 180° phase difference. This reduction in gain and phase errors in a satisfactory manner is a remarkable achievement, especially since it is achieved at 6-GHz microwave frequency range. By using the gm/ID methodology, a design flow is proposed in bulk- CMOS 65-nm technology. It enables us to identify, by identifying trade-offs in noise figure, gain, errors in output gain, and phases and components sizing, an appealing design region design.

ABSTRACT. An experimental study on the optimization of two-stage OTAs using different output stages and compensation techniques is presented. Optimization tries to maximize GBW for a given quiescent current consumption, and to this aim transistors are operating in weak inversion. A test chip prototype including 8 different two-stage OTA configurations has been fabricated in a standard 0.5-µm CMOS technology. Measurement results validate the benefits of the optimization technique employed in different design scenarios.

ABSTRACT. Climatological conditions study has gained interest nowadays due to their effect in human life quality. Air quality evaluation, both indoors and outdoors, is an important concern in cities, industries and workplaces. Sensors used for this task deliver small signals that need to be cleaned and processed. In this paper, the authors present a processing system based on a digital Lock-In amplifier for an NDIR CO2 sensor as part of a multi-sensor instrument capable of measuring different meteorological magnitudes. In space applications or IoT systems, it is important to consider factors such as maximum area, processing time and power consumption. To this purpose, two different implementations for the same processing system are presented, a purely hardware architecture and a software implementation on a soft-core microprocessor, based on the RISC-V, both on a Microsemi FPGA. Performance, resources usage and processing time are compared in both implementations in order to study their scalability towards a multi-sensor system.

ABSTRACT. Environmentally friendly devices production is increasing in today’s society due to the obvious need of a cleaner ambient, also, for the same reason of a necessity of a higher control of our surroundings, gas sensors have become important subject of research, especially lately with notably progress in low power photo-activated sensors. To contribute further with the development of eco-friendly devices, here we present a first prototype based on two ASICs developed in 180 nm with a low power consumption of 70 μW capable of driving and measuring a light-activated gas sensor at a sample rate of one second while sending the data through a Bluetooth transceiver. Due to the low power achieved, the system can be supplied by an energy harvester to make the device fully autonomous and self-sufficient.

ABSTRACT. This paper presents an algorithm to emulate in software the foveation mechanism to be implemented by an electronically foveated dynamic vision sensor. The algorithm has been applied for the foveation of recordings of Dynamic Vision Sensors observing dynamic scenes. The reduction in the number of events is demonstrated while preserving the original information in the detected regions of interest.

ABSTRACT. A digital signature is a cryptographic technique used to generate the signature of a message and verify the signature of that particular message. This signature scheme can ensure the validation of the authenticity, integrity, and non-repudiation of a message. Nowadays, the public-key cryptosystem RSA is widely used to perform the digital signature by using a public/private key pair. This paper describes the software and hardware hybrid implementation of the RSA digital signature on a System-on-Chip (SoC) that uses a RISC-V processor as processing core. The key generation for the RSA has been done in software, and the most time-consuming mathematical operation behind the RSA algorithm, the modular exponentiation, has been implemented in hardware. The proposed approach has been validated using one Xilinx Kintex-7 FPGA on the Genesys-2 FPGA board. The acceleration factor has also been calculated by comparing the software versus hardware implementation. The designed RSA IP has the flexibility to be reconfigured with different key sizes (512, 1024, 2048 bits) as per the requirements of the security level. The proposed implementation is verified using the National Institute of Standards and Technology (NIST) test vectors.

ABSTRACT. This paper describes two different approaches to emulate an Ethernet communication link between a host computer and a RISC-V multiprocessor system running on a FPGA accelerator by using PCIe as the real communication link. Two approaches are tested, one based on user-level applications using TUN/TAP drivers and another based on implemented kernel-mode drivers on the Linux Operation System. We have functionally validated the approaches in multiple RISC-V systems and measured the achieved performance. A maximum bandwidth of 32.5 Mbps has been achieved in a Lagarto Hun system running at 100 Mhz.

ABSTRACT. The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based hardware/software ecosystem has made it an attractive option for HPC application development and production. Within the field of biomedical research, genome data analysis has emerged as a crucial step towards personalized medicine, demanding substantial computational resources and more efficient tools.

This paper presents a benchmark suite of genome analysis kernels ported to RISC-V and their evaluation on modern RISC-V systems. Our work evaluates the RISC-V toolchain's maturity and the software/hardware ecosystem's readiness for its adoption for genome data analysis. This study aims to provide valuable guidance for researchers and practitioners interested in adopting RISC-V for genome analysis, and provides feedback to the RISC-V community on the challenges that need to be addressed for RISC-V to become an efficient HPC platform.

ABSTRACT. Networks of bipolar memristors have a rich collective switching behavior, which can be exploited in computing applications. Such a small network is formed by a pair of bipolar memristors connected in series or anti-series configuration. The latter is known as complementary resistive switch (CRS), and has been studied for memory and for logic applications. While CRS structures have been investigated with voltage-based driving schemes, the collective behavior of current-driven networks of memristors has not yet been explored. To this end, here we present preliminary experimental results from two bipolar self-directed channel (SDC) memristors by Knowm Inc., connected in series with the same or the opposite polarity, driven by current. The amplitude of the applied current pulses varied between |0.1 uA| and |1.0 uA|. The results demonstrate that current-based driving is effective for programming simultaneously memristors that are connected in series. Moreover, the devices in the CRS configuration respond in a complementary way to the applied input current. We observed a stable and uniform performance of the devices in all our experiments. Current pulses of |0.1 uA| did not affect the state of the memristors. So, they can be used for READ memory operations in current-driven resistive memory modules.

ABSTRACT. This paper presents the design of a scalable CMOS transistor array to characterize the active components of a standard 65 nm CMOS technology from room temperature down to the deep cryogenic regime. We present a system capable of individually characterizing up to 128 transistors of different sizes, using only 4 terminals corresponding to drain, source, gate and bulk, and a 7-bit demultiplexer to freely select the transistor to be characterized.

ABSTRACT. Biosignal acquisition has escaped hospital or laboratory environments to invade daily activities. Furthermore, the usefulness of these signals has been extended from just monitoring chronic patients to improving sport practices or to assure people's wellness. The arrival of wearable devices, built with smart sensors, high processing capabilities within tiny and attractive housings and user-friendly user interfaces, has fostered the applications where these signals are an important input, and which are helping people in an easy manner. However, the type of biosignals to be measured determines the location of sensors: the wrist is not always the best place to measure, and a smartwatch is not always the best wearable to use. In this scenario, skin patches appear to help in the sensing of bio-signals such as skin temperature (SKT), electrodermal activity (EDA), and blood volume pulse (BVP) among others. These patches should be built with flexible printed circuit boards (PCB) and, even, with flexible integrated circuits, to assure an easy adaptation to skin morphology. aIGZO (amorphous Indium Gallium Zinc Oxide) technology is a promising solution to explore new integration of analog-front-ends in biosignal acquisition and preprocessing. In this paper, different implementations of a ring oscillator (RO) as analog front-end to measure galvanic skin response (GSR) with aIGZO technology are analysed with regard to linearity, signal range, power consumption and area.

ABSTRACT. In the last years, the demand for positioning systems based on visible light, infrared light or, in general, optical signals has increased considerably due to their high accuracy and low cost compared to positioning systems based on other technologies, as well as their ease of integration due to their wide presence in domestic and industrial environments. The main constraint of these solutions is that the high speed of light makes the acquisition process complex. This work proposes a complete acquisition architecture for the twelve signals coming from four QADA (Quadrature Angular Diversity Aperture) photoreceptors, based on an analog front-end for signal conditioning at the input, an analog-to-digital converter, and a final digital stage using an FPGA for the acquisition of the data coming from the converter with high data rates up to 16.25 Msps. To verify the system performance, LS (Loosely Synchronized) sequences, often used in positioning systems, are emitted by a LED, and, later, they are acquired and digitally processed successfully by the proposed architecture in some preliminary experimental tests.

ABSTRACT. Contactless current sensing allows the measurement of energy consumption in electric and electronic circuits without the need of alter the structure of the system under study. For this purpose, contactless probes are based on the measurement of the magnetic field generated by the monitored current. Typically, for both AC and DC current sensing Hall-effect magnetic sensors are used. With a suitable configuration, portable low-cost Hall-based current probes can measure currents below 10 mA, suitable for energy monitoring in Internet of Things (IoT) devices, home appliances consumption, etc. However, for better response linearity and resolutions below 1 mA it is necessary to apply other solutions. This paper presents an analysis of the use of magnetoresistance devices based on quantum tunnel effect (TMR, tunnel magnetoresistance) to achieve these features. The main characteristics of a commercial low-cost TMR devices with a suitable resolution are measured, and compared to equivalent current sensing devices based on Hall-effect.

ABSTRACT. Iris recognition consists of measuring the unique patterns of the coloured and textured part of the eye (the iris), and comparing the obtained "signature" with those of a dataset to verify and authenticate identity. The uniqueness of the iris pattern makes the technique more robust and accurate for verification compared to other biometric systems. One of the main challenges of iris recognition is the ability to work with people on the move and at an increasing distance (over 1 metre). While the first implementations of iris recognition require the eyes to be placed at a close distance to the sensor and to maintain a static position during eye detection and capture, nowadays the iris recognition technique is progressing to be less intrusive. In this scenario, the problem of detecting the iris with an adequate quality (contrast, resolution) to be useful to identify the person, can force the framework to be able to process a large amount of frames per second (fps). This article describes the implementation in an MPSoC (Multiprocessor System-on-Chip) of a core that allows an eye detection framework to quickly evaluate the quality of the captured iris images. Thus, it is possible to remove the poor quality images from the subsequent processing steps. This implementation is intended to discard invalid images for person recognition therefore reducing the load on other parts of the system. It has been successfully integrated into an eye detection framework capable of processing over 50 fps working with a 16 Mpixel sensor.