Opening Session

IEEE CAS Distinguished Lecturer: Sudipto Chakraborty

Title: Ultra-low Power Cryo-CMOS Designs for Next-Generation Quantum Computing

This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

Keynote presentation: Davide Schiavone

Title: X-HEEP: A RISC-V Open-Source, Configurable, and Extendible Platform for Heterogeneous Ultra-Low-Power Edge-Computing Devices

After introducing the state of the art of open-source hardware/software and its importance and impact for growing all together in an open/collaborative way, we will introduce the platform X-HEEP (eXtendable Heterogeneous Energy-Efficient Platform).

X-HEEP is an open-source, configurable, and extensible single-core RISC-V microcontroller developed at the Embedded Systems Laboratory (ESL) of EPFL for edge-computing heterogeneous platforms. It is built on top of existing, mature open-source IPs from the OpenHW Group, the PULP team from ETH Zurich and the University of Bologna, and the lowRISC OpenTitan project and extended with custom blocks and logic to provide a system that can be easily extended via the X-HEEP interface with different accelerators, ranging from near/in-memory computing blocks, multicore systems, CGRAs, etc.

In this talk, we will show how X-HEEP can be configured to meet a wide range of requirements, how it can be extended with accelerators, and how it is used as a research platform for fast prototyping. We will show the results of our first prototype in TSMC65LP, where we used X-HEEP next to our CGRA, showing how X-HEEP and its interface can be efficiently exploited to build energy-efficient heterogeneous platforms.

In recent years, the importance of microchips has become increasingly evident. Although one trillion microchips were produced in 2020, this year witnessed the largest chip shortage to date, resulting in a significant spike in the cost of electronic devices. As a result, numerous sectors have been impacted, not just the automotive industry.  The importance of increasing semiconductor production capacity cannot be overstated, as recognized by the EU Council's approval of the European Chips Act on July 25. As part of a wider effort to boost digital innovation in Europe, the European Chips Act seeks to increase chip production with the goal of regaining Europe's sovereignty. Similarly, the federal CHIPS and Science Act in the United States offers billions of dollars in incentives for semiconductor manufacturing.

In this context, numerous funding opportunities exist for both companies and research institutions. Could this environment be the ideal place to foster collaboration between industry and academia? Representatives from administration, industry, and academia will discuss this topic.