Design-for-Test Strategies for Chiplets and Multi-Chip Module Integrations

EasyChair Preprint 15965

Abstract

This paper presents two advanced methodologies and three diagnostic approaches that significantly enhance Design-for-Test (DfT) capabilities in chiplet-based Multi-Chip Module (MCM) architectures. By leveraging machine intelligence and JTAG-compliant boundary scan infrastructure, the proposed strategies enable efficient identification and diagnosis of interconnect and functional faults in unknown dies. The combination of a twin-MCM test architecture, Connection Test Mode (CTM), and Wishbone-JTAG interfaces notably improves adaptive fault coverage and functional validation, particularly for modern chiplet-based automotive electronics.

Keyphrases: AI, Boundary Scan, Chiplets, DFT, FCT, IEEE1149, JTAG, KGD, MCM, Machine Intelligence, deep learning

@booklet{EasyChair:15965,
  author    = {Peter Wang},
  title     = {Design-for-Test Strategies for Chiplets and Multi-Chip Module Integrations},
  howpublished = {EasyChair Preprint 15965},
  year      = {EasyChair, 2025}}