CSD-Driven Speedup in RISC-V Processor

EasyChair Preprint 15796

Abstract

This paper introduces a synthesizable µ-architectural design method to boost the performance of a given RISC-V processor architecture by utilizing Canonical Signed Digit (CSD) representation during the execution stage within the processor pipeline. CSD is a unique ternary number system that enables carry/borrow-free addition/subtraction in constant time O(1) regardless of word length N. The CSD extension is exemplarily demonstrated to the Potato processor, a simple RISC-V implementation for FPGAs. However, the method can also be applied to other implementations in principle. Our performance boost due to the CSD requires an overhead for conversion between binary and CSD representation. This overhead is compensated by an extension to a seven-stage pipeline architecture, featuring a three-step execution stage that increases the throughput and the operating frequency and enables loop unrolling, which is especially advantageous in applications with consecutive calculations, e.g., signal processing. By experimental results, we compared our CSD-based ternary solution to the original implementation which utilizes the usual pure binary number representation of the operands. Our approach achieved a 2.41X increase in operating frequency over the original RISC-V processor on FPGA, with over 20% of this gain attributed to the CSD encoding. This enhancement resulted in up to a 2.40X improvement in throughput and a 2.37X reduction in execution time for computation-intensive benchmark applications.

Keyphrases: Canonical Signed Digit, FPGA, RISC-V, Ternary

@booklet{EasyChair:15796,
  author    = {Farhad Ebrahimiazandaryani and Dietmar Fey},
  title     = {CSD-Driven Speedup in RISC-V Processor},
  howpublished = {EasyChair Preprint 15796},
  year      = {EasyChair, 2025}}