An Asynchronous Matrix Multiplication Accelerator

EasyChair Preprint 13964

Abstract

Matrix multiplication plays an important role in various territories. The input data density leads to low computation efficiency, and synchronous circuits fail to meet the low-power requirement of specific fields. Therefore, an asynchronous matrix multiplication accelerator is proposed, which selects the appropriate calculation method by sensing the data density. For SpGEMM, a two-way condensation technique is adopted to solve the problem of spoiling the right matrix input reuse. An "one-to-one" merge strategy to reduce the uncertainty of the merge process is further proposed. Finally, the area of the accelerator is 17.3 $mm^{2}$, and the power demand is only 0.00468W in the UMC 110nm process. This research evaluates the accelerator on the SuiteSparse set and random matrix set, achieving 3.4× and 3.1× speed-up and 86× and 304× energy saving over MKL and cuSPARSE, respectively. It also achieves 62.3× and 11.25× energy saving over OuterSPACE and SpArch, respectively.

Keyphrases: Low-power Domain Architecture, asynchronous circuit, matrix multiplication

@booklet{EasyChair:13964,
  author    = {Lingzhuang Zhang and Rongqing Hu and Hongrui Zhang and Anping He},
  title     = {An Asynchronous Matrix Multiplication Accelerator},
  howpublished = {EasyChair Preprint 13964},
  year      = {EasyChair, 2024}}